Verilog-Perl

Here's some of the steps needed to add additional language syntax to the Verilog::SigParser.

First, thanks! It's wonderful to get new features contributed, as it's certain others have asked or will soon want exactly what you're working on.

Before editing, make sure you're using the git checkout so you have the latest code and can submit changes upstream (see Installing).

Next, add a test for the failing syntax (see the testing items in this forum, esp How to write a test.

Let's pick on "alias". Add to verilog/parser_bugs.v:

module bugalias;
  wire a;
  wire b;
  alias a=b;
endmodule

The t/35_sigparser test will now fail. Review any new keywords that will be needed, "alias" in this case.

In Parser/VParseLex.l, we'll need to change the following (Shown in diff format where + means add this, - means delete this):

-  "alias"        { FL; VALTEXT; CALLBACK(keywordCb); return ygenKEYWORD; }
+  "alias"        { FL; VALTEXT; CALLBACK(keywordCb); return yALIAS; }

Alias was returning a "generic keyword" token and now needs to be it's own token. We then need to add the token to Parser/VParseBison.y:

+  %token<str>        yALIAS        "alias" 

Now pull out the IEEE 1666 language spec and see how this fits into the grammar. Add appropriate grammar rules to Parser/VParseBison.y. See the forum topic on "Bison Parsing."

Fix the t/35_sigparser.t to pass (again see the testing items in the forum). Then get "make test" to pass. Review your changes with "git diff" then commit them "git ci -a" and submit them as a patch to the issue tracker here.

If you're biting off a very large task (like interfaces or such), I'd suggest starting with a small part of that task (say empty interfaces), write a test, fix the parser, make all tests pass, commit, then move on to something larger.