Verilator

Not currently, it's been asked several times, but no one has started code to my knowledge.

My intuition says there will be a decent, but not huge performance gain (peak of 10s not 100s), as GPUs don't like complex control flow nor non-symmetric data passing between threads. Most chip simulations consist of a lot of different operations with control flow differences and lots of interconnect, not small "kernels" of algorithms that repeat on a lot of data.

Of course some simulations are of chips with many parallel units, and it would better match such chips, but Amdahl's rule would still apply. Part of the work here is doing a good job of mapping the parallelism in the Verilog design (which isn't always obviously written that way) into parallelizable threads.

It will be interesting to see how the GPU compares with some of the new 12+ core multichip SMPs. There's also rumors of more "generic" integer GPGPUs coming in the future, which may be an even better match.

I'd be glad to provide pointers as to how to accomplish this. This is a fairly reasonable sized chunk of work; perhaps thesis worthy in itself; is that what you expect?