Verilator

Lane Brooks asked how to write a test.

The BUGS section of bin/verilator has instructions. Please feel free to send edits or edit that yourself with additional notes.

The basic idea is the Verilog is generally self-testing. On fail it prints a message and calls $stop. On pass it calls

$write("*-* All Finished *-*\n");
$finish;

You can run a test on Cadence NC Verilog (ncv) or Synopsys VCS by running

cd test_regress
t/t_TESTNAME.pl --nc
t/t_TESTNAME.pl --vcs

You may need minor edits to get this working depending on how you have their programs installed. If you have the GIT checkout, the nodist/invoke_ wrappers are used to solve some of these issues. (If it's the tar'ed kit, these wrappers are skipped and its assumed the NCV files are in your PATH.)

You can run all tests with

make test

in the top directory. If it's getting too slow it understands how to use multicore; ask for instructions as some additional Perl modules are needed.

The instructions assume the default .cpp top level file; if you need a custom file search for other tests with a .cpp in test_regress/t for example t_func_rand.cpp. Then if you look at t_func_rand.pl you can see the magic for a test with a custom top:

compile (
      make_top_shell => 0,
      make_main => 0,
      v_flags2 => ["--exe t/$Last_Self->{name}.cpp"],
      ) if $Last_Self->{v3};