TriState Implementation

Added by Dennis Muhlestein over 3 years ago

Suppose I have two modules which have inout data for a wire.

Verilator will compile the following:

wire data;

module1 m1 ( data );
module2 m2 ( data );

but not the following:

wire d1, d2;
assign d1=d2;
module m1 (d1);
module m2 (d2);

In the latter case, I get an unsupported high-Z construct error. This was part of the problem I was trying to fix yesterday when I wanted to raise the debug level by the way. The error does not print the name of the inputs that are having the problem, the file, or the line number.

In general would you prefer discussion of issues like this 1st or simply filing an issue?

Replies (2)

RE: TriState Implementation - Added by Wilson Snyder over 3 years ago

I'd say if it's a specific problem like this a bug is better.

BTW are you sure assign works to pass data both ways in this context versus using the SystemVerilog "alias" statement (which certainly would work)?

RE: TriState Implementation - Added by Dennis Muhlestein over 3 years ago

Maybe I shouldn't file a bug until we look it up in a spec somewhere. It seems like it should work though. We're using this in a few places in our FPGA Verilog and haven't noticed any issues.

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