Verilator

Hi,

We have success verilated our design and the verilated model passed simulations. However, we found one issue regarding the reset values of asynchronous resettable flops:

The verilated flop will not reset to the reset value unless a reset_n negedge or a clock posedge is triggered. This will become a problem when 1. flop does not receive clock during reset 2. AND the initial value of reset_n is 0 (no negedge)

In our case, we have (1) because the flop is clock-gated, and (2) because reset is generated from verilog testbench which has been relying on 4-state simulation where x->0 is counted as negedge.

We are currently working around this problem by changing the reset generation to create a 1->0 negedge in the testbench but we are wondering if it makes sense to initialize the flop output to the reset value (see below)

Given a flop below:

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module flop(qqqq, d, clk, reset_n); output [2:0] qqqq; input [2:0] d; input clk; input reset_n; reg [2:0] qqqq; always @(posedge clk or negedge reset_n) begin if (!reset_n) begin qqqq <= 3'b101; end else begin qqqq <= d; end end endmodule

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The verilated code below:

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void Vflop::_sequent__TOP__3(Vflop__Syms* __restrict vlSymsp) { VL_DEBUG_IF(VL_PRINTF(" Vflop::_sequent__TOP__3\n"); ); Vflop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body // ALWAYS at flop.v:8 vlTOPp->_Vcellinp_v__qqqq = ((IData)(vlTOPp->_Vcellinp_v__reset_n) ? (IData)(vlTOPp->_Vcellinp_v__d) : 5); VL_ASSIGN_SII(3,vlTOPp->qqqq, vlTOPp->_Vcellinp_v__qqqq); }

void Vflop::_eval(Vflop__Syms* __restrict vlSymsp) { /* ... */ if ((((IData)(vlTOPp->Vcellinp__v__clk) & (~ (IData)(vlTOPp->_Vclklast_TOP_Vcellinp_v__clk))) | ((~ (IData)(vlTOPp->VinpClk__TOP_Vcellinp_v__reset_n)) & (IData)(vlTOPp->Vclklast__TOP_VinpClk_TOP____Vcellinp__v__reset_n)))) { vlTOPp->sequent_TOP__3(vlSymsp); } /* ... */ }

/* constructor */ VL_SC_CTOR_IMP(Vflop) { //... // Reset structure values _Vcellinp_v__qqqq = VL_RAND_RESET_I(3); }

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From the verilated code above, "__Vcellinp__v__qqqq" is initialized to either (0) or random value initially and it will need a real 1->0 reset edge or a clock edge to get to settle to the proper reset value. This behavior is a little bit different than the actual hardware where we expect the reset value to be 3'b101 as soon as reset_n is 0 without clocks.

However, if "__Vcellinp__v__qqqq" is initialized to the actual reset value, the generated flop behavior could match the actually hardware. I wonder if it makes sense to do this change.