Verilator

Only "structs, enumerated types, packed arrays, packages and namespaces?" :)

I'd love a contribution of code to support one or more of those. Baring assistance, I expect to add SystemVerilog support as time permits. As my current project doesn't need them it's probably a year before I'd need to get all of these items in.

Relatedly, over the next twoish months I'd like to add full SystemVerilog parsing to Verilog-Perl. This is a first step as it shares a front end with Verilator. If you could send me code off line I'd appreciate it, as I've found very few SystemVerlog examples in the wild to start testing with.

Hi, I'm working on a project that requires SystemVerilog support. How difficult do you think it would be for me to start adding support? What sort of knowledge would be required? I've had a quick look at the Verilator code Lex and Yacc stuff but can't see where to go after that.

I and many other people would love help adding more SV support.

The Verilator parser doesn't support more SV only because the rest of the program doesn't support more SV. The Verilog-Perl parser now fully supports SystemVerilog, so this means adding bison/lex support in Verilator is a fairly easy job of cut (from Verilog-Perl) and paste (to Verilator) as two parsers track each other. In many cases I've already pasted the code and commented it out.

The work then is in creating a AST (abstract syntax tree) class for whatever new feature(s) are desired, then handling the new AST nodes in the rest of the program.

It's generally easiest to pick a feature and add them one by one, rather than getting drowned by adding a lot at once. Any idea where would you like to start? From there I can describe further what would be needed.

interface and logic are probably the ones we use the most so would probably start there.

There's two parts to logic - the simple way would be to add it to the parser than treat it just like a reg - that'll mostly work. The harder stuff is to support it as a real type. I'd suggest the first approach.

Interface isn't too bad either, but requires touching more code.

So, if you're game, I'd say first file a bug here asking to "support logic" then I'll suggest what to do there. It's hopefully only a few hour project; maybe a little more as you need to learn the code.

I have to head out now for most of the rest of the day, but if you want to start look at Verilog-Perl to see how it deals with LOGIC - note the type handling isn't done the same way in Verilator yet. Also throw together a test case or two - see the docs and t/t_EXAMPLE.* for how to do it.

Hi, I've added the issue to the tracker.

What is the status of support for SystemVerilog features?

Are there any plans to support structs?

The reason I am asking about structs is because Altera DDR3 DRAM behavioral model uses structs and I would like to use it as is without rewriting.

It's very ill advised for a design IP vendor to use a SV feature.

Anyhow, there is a partial patch that does all of the parsing, but doesn't complete expanding the structs. I'm unlikely to work on it in the next month. If you have time to work on it I can send it across.

What about SV const? I.e. something like const logic [3:0] ...

const is reasonable I'll work on it.

BTW const logic is in 3.820.

Thanks a lot!

Support of real numbers is also very helpful.