Clock generator

Dear All,

I want to generate a clock pulse. In verilog we do it: always #(clock_time/2) clk= ~clk

The code is compile in Verilog Icarus. However, it Verilator using -sc options, gives an error message.

Best regards, Yehuda

Replies (1)

RE: Clock generator - Added by Wilson Snyder 3 months ago

Sorry, but Verilator isn't a full testbench simulator, see the Intro. It doesn't have events; clocks are driven in from the SystemC or C++ wrapper, or derived with logic from clocks from SystemC or C++.

(1-1/1)