Top level

dear All, suppose we have a design composed of files A,B and C where A is the top level. Modules in files B and C are instantiated in A.We want to generate SystemC files.

For B and C we use: verilator -sc B.v and verilator -sc C.v For A we tried verilator -sc --top-level A.v. THis does not work.

Best ergadrs, Yehuda

Replies (1)

RE: Top level - Added by Wilson Snyder 3 months ago

Verilator does the whole hierarchy at once for speed: verilator -sc A.v B.v C.v

However if you have your +incdir and/or -y path specified, as with most simulators, Verilator will find B & C by itself, so you only need A.v on the command line.

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