Verilator

One observation is that, although using non-blocking assignments in combinatorial code is bad practice, it is legal Verilog. Should we really be treating the first block as though it were clocked sequential logic:

always @(posedge clk or negedge clk) begin
   if (clk) begin
      y1 <= 1'b0;
   end
   else begin
      y1 <= 1'b1;
   end
end

What exactly does design compiler do with this in terms of the gates it generates? I'm skeptical there's an easy fix here, but perhaps there's some pattern that can be easily recognized like design compiler does.

The synthesized module is an inverter feeding into a D-type flip-flop:

module sim_top ( clk, ctrl );
  input clk;
  output ctrl;
  wire   y1;

  DFFQX1 y2_reg ( .D(y1), .CK(clk), .Q(ctrl) );
  CLKINVX1 U4 ( .A(clk), .Y(y1) );
endmodule

I've attached a PDF of the schematic.

I understand the PDF may not display/print properly using evince on Linux. I attach a PostScript version to this message.

module sim_top (clk , ctrl);

   input wire clk;
   output wire ctrl;

   reg            y1;
   reg            y2;

   assign ctrl = y2;

   always @(clk) begin
      if (clk) begin
         y1 <= 1'b0;
      end
      else begin
         y1 <= 1'b1;
      end
   end

   always @(posedge clk) begin
      y2 <= y1;
   end

endmodule

Assuming we have clk==1, then when clk goes low we eventually get

clk==0 && y1==1'b1

then when clk goes high we get

clk==1 && y1==1'b1 && y1'==1'b0 && y2'==(y1)

where y1' is the uncommitted non-blocking assignment update, which is

clk==1 && y1==1'b1 && y1'==1'b0 && y2'==(1'b1)

so eventually we have

clk==1 && y1==1'b0 && y2==1'b1

so y2 latches hi (as we describe the other tools doing?). If we observe correct non-blocking assignment timing. ie on a posedge, y1 is not yet low when y2 samples.

So it seems that Verilator's treatment of -Wno-COMBDLY by replacing all non-blocking assignments in combinatorial blocks by blocking assignments causes some code to simulate incorrectly. The solution is for -Wno-COMBDLY to correctly model NBA. I am not sure if a quick(er) fix to this is for all sensitivities in blocks with non-blocking assigments to be treated as edges (positive and negative) rather than combinatorial activity.

I believe we can achieve the required result by a rewrite. The original code, which triggers COMBDLY, is:

   always @(clk)
     begin
        if (clk) begin
           y1 <= 1'b0;
        end
        else begin
           y1 <= 1'b1;
        end
     end

   always @(posedge clk) begin
      y2 <= y1;
   end

We can replace this by

   initial begin
      y1_tmp = 1'bx;
   end

   always @(clk)
     begin
        if (clk) begin
           y1_tmp = 1'b0;
        end
        else begin
           y1_tmp = 1'b1;
        end
     end

   always @(posedge y1_tmp or negedge y1_tmp) begin
      y1 <= y1_tmp;
   end

   always @(posedge clk) begin
      y2 <= y1;
   end

This is compilable by Verilator without complaint and yields the expected behavior (the initial setting to 1'bx is required to ensure the first edge is picked up). Although presented as a source level rewrite, it can be implemented as an AST edit in V3Active.cpp, conditional on the use of -Wno-COMBDLY. I shall work on an implementation.

This rewrite doesn't work if y1 is more than 1 bit wide. For example:

   reg [1:0] y1;
   reg [1:0] y2;

   always @(clk)
     begin
    y1 <= {clk, ~clk};
     end

   always @(posedge clk)
     begin
        y2 <= y1;
     end

   reg [1:0] y1;
   reg [1:0] y1_tmp;
   reg          y1_latch;
   reg [1:0] y2;

   always @(clk) begin
      y1_tmp = {clk, ~clk};
      y1_latch = 1'b0;
   end

   always @(y1_tmp) begin
      y1_latch = 1'b1;
   end

   always @(posedge y1_latch) begin
      y1 <= y1_tmp;
   end

   always @(posedge clk) begin
      y2 <= y1;
   end