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	#	Project	Tracker	Status	Priority	Subject	Assignee	Updated
	437	Verilog-mode	Issue	New	Normal	Indentation of continued assignment incorrect if first line ends with ']'		02/03/2012 02:38 pm
	435	Verilog-mode	Issue	New	Normal	Indenting comments on declarations in v736		02/02/2012 09:07 pm
	433	Verilog-mode	Issue	New	Normal	indenting for some forms of SystemVerilog constraints is wrong/odd		01/27/2012 10:52 pm
	432	Verilator	Issue	Resolved	Normal	Internal Error with large amount of UNOPTFLAT Warnings	Wilson Snyder	01/27/2012 01:20 am
	431	Verilator	Issue	AskedReporter	Normal	typedef inside module causes internal error	Wilson Snyder	01/12/2012 12:51 am
	430	Verilog-mode	Issue	New	Normal	Incorrect indentation in Verilog Mode v736	Michael McNamara	01/10/2012 12:45 pm
	427	Verilog-mode	Issue	New	Normal	alignment in always @(*) blocks behaves strangely	Michael McNamara	01/02/2012 05:05 pm
	426	Verilog-Perl	Issue	Feature	Normal	Add ability to not process some `ifdefs		12/23/2011 02:48 pm
	424	Verilator	Issue	Feature	Normal	Multiple problems encountered with parameter arrays		12/15/2011 12:16 pm
	421	Verilator	Issue	Feature	Normal	Add an option for a custom header comment	Jeremy Bennett	11/17/2011 09:02 am
	419	SVN::S4	Issue	New	Normal	s4 update fails to remove a view when it is removed from viewspec	Wilson Snyder	11/09/2011 12:39 pm
	418	SVN::S4	Issue	New	Normal	aliased entries in s4_state cause warnings on s4 update	Wilson Snyder	11/07/2011 06:41 pm
	417	SVN::S4	Issue	New	Normal	Potential new s4 commands: doview and unview	Wilson Snyder	11/07/2011 06:13 pm
	416	SVN::S4	Issue	New	Normal	s4 view command support for regexps at multiple levels of directory hierarchy	Wilson Snyder	11/07/2011 06:00 pm
	413	Verilator	Issue	Feature	Normal	generate-conditional with short-circuited local expression		11/15/2011 11:14 am
	408	Verilator	Issue	Assigned	Normal	verilator generates incorrect C++ code when genvar is used incorrectly		11/12/2011 01:11 pm
	406	Verilator	Issue	Feature	Normal	delayed assignment of unsized constant fails	Jeremy Bennett	11/29/2011 02:18 am
	399	Verilog-mode	Issue	Resolved	Normal	alignment of assignment operators and comparison operators	Michael McNamara	12/15/2011 06:46 pm
	395	Verilator	Issue	Assigned	Normal	Tristate pins again	Lane Brooks	10/04/2011 01:27 pm
	393	Verilator	Issue	Assigned	Normal	%Error: Internal Error: ...: ../V3AstNodes.h:453: Unexpected Call	Wilson Snyder	09/21/2011 11:30 pm
	392	Verilator	Issue	Assigned	Normal	Can't unroll generate for with complicated incrementer	Wilson Snyder	09/19/2011 02:51 pm
	387	SystemPerl	Issue	Assigned	Normal	system perl cannot handle 2 uses of SP_TEMPLATE	Wilson Snyder	09/28/2011 11:13 am
	386	Verilog-mode	Issue	New	Normal	Indenting of user-defined data types		02/05/2012 02:35 am
	385	Verilator	Issue	Feature	Low	Dpi exported tasks with array inputs don't compile.	Wilson Snyder	11/29/2011 03:13 am
	380	Verilator	Issue	Assigned	Normal	Support of VHDL93	Sebastien Van Cauwenberghe	08/10/2011 06:49 am

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