Verilog-mode

I've recently moved from using old Verilog Mode v357 to v528. Immediately I have noticed that the code indenting no longer works as it used to. This may be a deliberate change, but personally I preferred the old way and can't see any advantage to it, so I think this change is a bug.

So here's an example of what I'm talking about. I just started a new module, and the first few lines of code look like this:

module soft_rst
  (
   // System clock and reset
    input           clk,
    input           rst_n,

   // Interface to software land
    input           req_soft_rst,   // Soft reset request
    output          soft_rst_dne,   // Soft reset done

   // Interface to other modules
    output          dma_halt,       // Reset pending, halt activity
    input           tx_quiet,       // TX side is dormant
    input           rx_quiet,       // RX side is dormant
    output       soft_rst,       // Soft (sync) reset to VC3 side
    output       hs_async_rst_n  // Async reset to host side
   );

   reg [1:0]     state;

   localparam [1:0] IDLE = 2'h0,
     HALT = 2'h1,
     RST  = 2'h2,
     DONE = 2'h3;

endmodule // soft_rst

Notice that the last two output assignments and the last three localparams aren't aligned with the declarations above. If I run indent-region on this (C-M-\), or equivalently press TAB the lines that aren't yet aligned, in Verilog mode v357 it turns into this:

module soft_rst
  (
   // System clock and reset
    input           clk,
    input           rst_n,

   // Interface to software land
    input           req_soft_rst,   // Soft reset request
    output          soft_rst_dne,   // Soft reset done

   // Interface to other modules
    output          dma_halt,       // Reset pending, halt activity
    input           tx_quiet,       // TX side is dormant
    input           rx_quiet,       // RX side is dormant
    output          soft_rst,       // Soft (sync) reset to VC3 side
    output          hs_async_rst_n  // Async reset to host side
   );

   reg [1:0]        state;

   localparam [1:0] IDLE = 2'h0,
                    HALT = 2'h1,
                    RST  = 2'h2,
                    DONE = 2'h3;

endmodule // soft_rst

but in v528 it doesn't.

I've tried this in a vanilla emacs (-no_init_file -no-site-file) and the result is the same.

Emacs : GNU Emacs 21.3.1 (x86_64-unknown-linux-gnu, X toolkit, Xaw3d scroll bars) of 2006-09-26 on mon-irva-35

Thanks for Verilog Mode!