![[logo]](/img/veripool_small.png)
Issue #14
Verilator Doesn't catch duplicate declaration of signal
| Status: | Closed | Start date: | 06/19/2008 | ||
|---|---|---|---|---|---|
| Priority: | Normal | Due date: | |||
| Assignee: | - | % Done: | 20% |
||
| Category: | Lint | ||||
| Target version: | - |
Description
The attached Verilog file declares the signal "clk" twice, once as an input and once in the body, but no error message is displayed.
A more complicated module with this bad design resulted in error messages that didn't make sense (modules not being recognized or required).
History
Updated by Wilson Snyder almost 4 years ago
- Category set to Lint
- Status changed from New to Assigned
- % Done changed from 0 to 20
I looked into this, and don't see how it should cause a downstream problem, are you sure this fixed it? I think the only difference I see in the result could also occur using verilog 2001 "input wire" without a second wire statement.
I've held off putting it into 3.665 as I'm going to be changing a bunch of this code soon, so it'll be in 3.666 or whatever is next.
Updated by Wilson Snyder almost 4 years ago
- Status changed from Assigned to Closed
As you noted, this is ugly, but very hard to fix at this point as everything is tracked by signal, not bit. Someday.
Also available in: Atom