Verilog-Perl

%Error: test1.v:30: syntax error, unexpected '[', expecting IDENTIFIER or '='

module lib_add_bintree
#(parameter
    // Number of input values
      NUM       = 9
    // Width of each value
    , WIDTH     = 8
) (
    // Values to add
      input  logic  [NUM-1:0][WIDTH-1:0]    a
    // Resulting sum
    , output logic  [WIDTH-1:0]             sum
);

typedef logic [WIDTH-1:0] val_t;

localparam NLOG =
                  (NUM <=     2) ?  1
                : (NUM <=     4) ?  2
                : (NUM <=     8) ?  3
                : (NUM <=    16) ?  4
                : (NUM <=    32) ?  5
                : (NUM <=    64) ?  6
                : (NUM <=   128) ?  7
                : (NUM <=   256) ?  8
                : (NUM <=   512) ?  9
                : (NUM <=  1024) ? 10
                : 0;

// binary search tree
val_t [NLOG:0][NUM-1:0] tree;
endmodule