Verilog-Perl

I'm sorry about this but I'm not under NDA with your company and we both need to honor the copyrights in the files, unless you can state you own the copyright - and no it's not enough to just strip the comments :) I'm deleting them.

I think there's real issues here, but I really need a issue for each major problem including a "sanitized" few lines of each construct that is causing problems. For example from what you emailed separately:

module bugas;
   initial begin
      ASSERT_CHK: assert (0) else $error("%m -- not allowed %d", 0);
   end
endmodule

Sorry, but this is part of the "cost" to you of open source.