Verilog-Perl - Issue #191: Define with formal matching $pli call gets misexpanded - Veripool

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Issue #191

Define with formal matching $pli call gets misexpanded

Added by Wilson Snyder 9 months ago. Updated 9 months ago.

Status:

Closed

Start:

11/23/2009

Priority:

Normal

Due date:

Assigned to:

% Done:

0%

Category:

-

Target version:

-

Description

`define foo(bits) $display("bits %d %d", $bits(foo), `bits)

`foo(10) gives

$display("bits %d %d", $10(foo), 10);

Note $bits was misexpanded.

History

#1
Updated by Wilson Snyder 9 months ago

Status changed from New to Resolved

Fixed in git for 3.222++.

#2
Updated by Wilson Snyder 9 months ago

Status changed from Resolved to Closed

In 3.222.

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