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Issue #202

verilog parser error

Added by Rick Ramus over 2 years ago. Updated about 2 years ago.

Status:Closed Start date:01/11/2010
Priority:Normal Due date:
Assignee:Wilson Snyder % Done:

0%
Category:-
Target version:-

Description

module top (out,in); 

output [3:0] out;
input [3:0]  in;
node [2:0] int;

`define BUF(out,in)                                                   \
   assign out = in ;                                                  \
`endif

 `BUF(int, in[2:0])
 `BUF(out, {in[3], int})

endmodule

produces the following error: %Error: <verilog_path>/top.vs:13: Define passed wrong number of arguments: BUF

History

#1
Updated by Wilson Snyder over 2 years ago

  • Status changed from New to Resolved

Ignoring the extra `endif and that int is a reserved word, I think this was fixed a week ago when System Verilog 2009 `define enhancements were put in. Please try the git version and let me know.

That will be in the next release, another week or so.

#2
Updated by Wilson Snyder over 2 years ago

  • Status changed from Resolved to Closed

In 3.230.

#3
Updated by Rick Ramus over 2 years ago


`define FC_INV(out, in)                                                   \
`ifdef MACRO_ATTRIBUTE \
  (* macro_attribute = `"FC_INV (out``,in``)`" *) \
`endif \
  assign out = ~in ;

`define FC_INV1(out, in)                                                   \
`ifdef DC                                                                     \
     yg0inn30nn1g7 \fc_inv_``out <$typeof(out)> (.a(<in>), .o(<out>));   \
  `else                                                                         \
   `ifdef MACRO_ATTRIBUTE \
      (* macro_attribute = `"FC_INV (out``,in``)`" *) \
   `endif \
   assign out = ~in ;                                                \
`endif

`define FC_INV2(out, in)                                                   \
`ifdef DC                                                                     \
     yg0inn30nn1g7 \fc_inv_``out <$typeof(out)> (.a(<in>), .o(<out>));   \
      /* comment */ \
  `else                                                                         \
   `ifdef MACRO_ATTRIBUTE \
      (* macro_attribute = `"FC_INV (out``,in``)`" *) \
   `endif \
   assign out = ~in ;                                                \
`endif

`define FC_INV3(out, in)                                                   \
`ifdef DC                                                                     \
     yg0inn30nn1g7 \fc_inv_``out <$typeof(out)> (.a(<in>), .o(<out>));   \
      /* multi-line comment \
         multi-line comment */ \
  `else                                                                         \
   `ifdef MACRO_ATTRIBUTE \
      (* macro_attribute = `"FC_INV (out``,in``)`" *) \
   `endif \
   assign out = ~in ;                                                \
`endif

produces the following error: %Error: <verilog_path>/top.vs:29: Internal Error: VPreproc.cpp:695: Bad define text Stopped at <path>/Verilog/Parser.pm line 179

I ran with recently released Verilog-Perl version 3.23

#4
Updated by Wilson Snyder over 2 years ago

Works for me, maybe you're not really getting the version you think?

perl -e 'use Verilog::Language; print $Verilog::Language::VERSION'

Here's what I get

$ ./vppreproc -DMACRO_ATTRIBUTE a.v
...
 (* macro_attribute = "FC_INV (a,b)" *) assign a = ~b ;
 (* macro_attribute = "FC_INV (a1,b1)" *) assign a1 = ~b1 ;
 (* macro_attribute = "FC_INV (a2,b2)" *) assign a2 = ~b2 ;
 (* macro_attribute = "FC_INV (a3,b3)" *) assign a3 = ~b3 ;

$ ./vppreproc -DDC a.v
 assign a = ~b ;
 yg0inn30nn1g7 \fc_inv_a1 <$typeof(a1)> (.a(<b1>), .o(<a1>));
 yg0inn30nn1g7 \fc_inv_a2 <$typeof(a2)> (.a(<b2>), .o(<a2>));
 yg0inn30nn1g7 \fc_inv_a3 <$typeof(a3)> (.a(<b3>), .o(<a3>));

# The <>'s seem like mistakes in your example.

#5
Updated by Wilson Snyder over 2 years ago

  • Status changed from Closed to Assigned
  • Assignee set to Wilson Snyder

(Offline test case sent)

Thanks for the testcase, now I see that what is needed to expose it the default stripping of comments. I'll fix it asap as I think it's simple. Meanwhile a simple workaround for the current release is:

my $nl = Verilog::Netlist->new (options => $opt, keep_comments=>1);

#6
Updated by Wilson Snyder over 2 years ago

  • Status changed from Assigned to Resolved

Fixed in git for next release, 3.231+.

#7
Updated by Wilson Snyder about 2 years ago

  • Status changed from Resolved to Closed

In 3.231.

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