Support assignment between packed arrays with different dimensions
|Assignee:||Byron Bradley||% Done:||
Verilator doesn't support:
logic [1023:0] data_conc; logic [31:0][31:0] data; assign data = data_conc;Slice support in issue #170 comes very close to this. Remove the checks to detect it as an error and it just needs to figure out that it is packed and to set the bits in the Sel node on data_conc appropriately for each element in data. This probably needs a very strict check that the number of packed bits is equal on both sides.
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