Verilator

Signals in a concatenation on the LHS aren't created implicitly, e.g.:

    logic [1:0] dummy_ip;
    assign {dummy1, dummy2} = dummy_ip;

Fails to create dummy1 and dummy2. Test case and proposed patch attached, I originally just checked for VarRefs in op¹²³⁴p but didn't see any harm in calling pinImplicitExprRecurse() instead.