Bitwise reductions on signals with >1 packed dimension generates incorrect code
|Assignee:||Byron Bradley||% Done:|
logic [3:0][7:0][1:0] vld; assign vld_or = |vld;gets treated as a normal slice and generates incorrect code. I have this working and will submit patches tomorrow, just need to do some more verification. The changes are mostly to V3Slice with some small changes elsewhere to differentiate between packed and unpacked dimensions.
#1 Updated by Byron Bradley over 3 years ago
- File 0001-Mark-packed-dimensions-in-arrays.patch added
- File 0002-modify-AstVar-dimensions-to-return-a-pair.patch added
- File 0003-Support-reduction-operations-on-multiple-packed-dime.patch added
- Add isPacked() to AstArrayDType().
- Modify AstVar::dimensions to return a pair of packed/unpacked dimensions.
- Support the reduction operators (or, and, xor, xnor) in V3Slice. This includes a bug-fix to the ordering of dimensions to insertImplicit().
#3 Updated by Byron Bradley over 3 years ago
- File 0004-Fix-slices-over-non-reduction-unary-operations.patch added
- Status changed from Resolved to Assigned
logic [3:0][7:0][1:0] not_lhs; logic [3:0][7:0][1:0] not_rhs; assign not_lhs = ~not_rhs;Fix and test-case attached.
#4 Updated by Wilson Snyder over 3 years ago
If we start needing to do more things on AstRed* it's better to make them each a subclass of a new AstNodeRed or somesuch, which in turn is a AstNodeUniop. It's not worth it for this one use though.
BTW sorry I botched your name, I'm trying (and obviously failing to) train myself to always cut-and-paste names rather than type...