Issue #229: assert syntax errors - Verilog-Perl - Veripool

Issue #229

Status:

NotEnoughInfo

Start date:

03/31/2010

Priority:

Normal

Due date:

Assignee:

% Done:

Category:

Target version:

Description

For the following assert statement: `define ASSERT1 assert final(rst || $onehot0(sig)) `ASSERT1

I get the following error: Syntax error, unexpected "final", expecting "property"

For the following assert statement: `define ASSERT2 assert property(never(prop, clk, rst)) `ASSERT2

I get the following error: Syntax error, unexpected "posedge", expecting "CLASS-IDENTIFIER" or "COVERGROUP-IDENTIFIER" or "TYPE-IDENTIFIER"

Unless I'm missing something, assert final isn't legal syntax.

The second isn't the complete example because there's no posedge in what you sent, send a full case.

Assuming this is ok now.

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