![[logo]](/img/veripool_small.png)
Issue #233
Support real numbers
| Status: | Closed | Start date: | 04/07/2010 | |
|---|---|---|---|---|
| Priority: | Normal | Due date: | ||
| Assignee: | - | % Done: | 0% |
|
| Category: | Unsupported | |||
| Target version: | - |
Description
Filing separate bug as mentioned in bug223. This is a pre-requisite to finally support timing events, loops and behavioral events.
History
Updated by Wilson Snyder about 3 years ago
- Category set to Unsupported
- Status changed from New to Feature
Notes from the standard:
3.5.3 Conversion
Real numbers shall be converted to integers by rounding the real number to the nearest integer.
4.1 Value set
The default initialization value for real is 0.0.
realtime === real
4.8.1 Operators and real numbers
Real numbers prohibited:
Edge descriptors (posedge, negedge) applied to real variables
Bit-select or part-select references of variables declared as real
Real number index expressions of bit-select or part-select
Implicit conversion shall take place when an expression is assigned to a
real. Individual bits that are x or z in the net or the variable shall be
treated as zero upon conversion.
5.1.1 Operators with real operands
unary + unary - Unary operators
+ - * / ** Arithmetic
> >= < <= Relational
! && || Logical // via comparison with 0.0
== != Logical equality
?: Conditional
If either operand of the power operator is real, then the result type shall
be real. The result of the power operator is unspecified if the first
operand is zero and the second operand is nonpositive or if the first
operand is negative and the second operand is not an integral value.
RELATIONAL/EQUALITY:
If either operand is a real operand, then the other operand shall be
converted to an equivalent real value and the expression shall be
interpreted as a comparison between real values.
If any operand is real, the result is real.
$display - just use printf
%e or %E Display 'real' in an exponential format
%f or %F Display 'real' in a decimal format
%g or %G Display 'real' in exponential or decimal format, which-
ever format results in the shorter printed output
System tasks that need compiler support
$realtime
integer $rtoi(real_val) ;
real $itor(int_val) ;
[63:0] $realtobits(real_val) ;
real $bitstoreal(bit_val) ;
Rest can probably wait.
Updated by Wilson Snyder about 3 years ago
Real numbers are probably a week's work, they aren't too bad, it's mostly lots of boilerplate to add the various operators and optimizations, and testing.
0. Extend test_verilated/vgen.pl to generate floating point numbers. Since floats are represented the same in both Verilog and Perl this is hopefully just a matter of adding new Ops for each floating point operation. Test that it generates good tests on other simulators. (It's important to have generated tests as it's much less time than debugging subtle arithmetic optimization errors.)
The strategy I then use is generally to get the test further and further down the compiler steps, till there's finally emitted code.
1. Add lexing and parsing of "real" (copy how the other data types work). "realtime" and "shortreal" can alias to "real" - that's what most other simulators do anyhow.
2. Reals create AstBasicDTypeKwd REAL - that already exists. I'm thinking the values are represented just as if they were 64-bit vectors, it's just how they add/subtract etc that changes.
3. Add floating operations to V3Number, for example V3Number::opAddF - these take two 64-bit vectors and using a union convert them to doubles then union them back.
4. Add floating operations Ast types to V3Ast, for example AstAddD. (D for double.) This just calls the new V3Number operations.
5. (The real work) Add a stage similar to V3Signed to determine what ast nodes are real operations and convert AstAdd to AstAddD, etc.
6. Add additional floating optimizations to V3Const. For example "AstAdd{$lhsp, $rhsp.isZeroD} -> $lhsp" IE (n+0==n). This can probably mostly wait as later optimization, though a few may be needed to get things to work - for example AstRToI and AstIToR should be implemented so a constant float can become a constant non-float and vice-versa.
7. Probably minor changes needed to many of the middle stages, but I don't think there's anything major.
8. Teach V3EmitC how to print "double" and any new PLI tasks. Most of this will come from the earlier edits, as the new Ast Types can describe how to print the operations.
9. Add any new runtime operations to verilated.h. The main obvious one would be $display of floats and RToI and IToR (using a union).
Ask as you hit issues.
Updated by Alex Solomatnikov over 1 year ago
verilator does not support $ceil() function which is part of SystemVerilog standard:
%Error: ...: Unsupported or unknown PLI call: $ceil %Error: Exiting due to 1 warning(s) %Error: See the manual and http://www.veripool.org/verilator for more assistance.
VCS compiles $ceil().
Updated by Wilson Snyder over 1 year ago
$ceil and friends are now in git. BTW if you don't mind please file new bugs, otherwise I'm likely to miss the issue since the old bug is closed, thanks.
Also available in: Atom