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Issue #241
defparam keywork in verilog
| Status: | WillNotFix | Start date: | 04/12/2010 | |
|---|---|---|---|---|
| Priority: | Normal | Due date: | ||
| Assignee: | Wilson Snyder | % Done: | 0% |
|
| Category: | Usage | |||
| Target version: | - |
Description
Hi
I have verilated my RTL verilog code which has certain parameters defined by keyword parameter in verilog which are to be
passed by top module.
I am writing now the top module in systemC by instantiating the verilated verilog code as submodule.
I want to pass those parameters from top level systemC to my instantiated verilog code in the same way as defparam keyword
in verilog does so.
What is the appropriate way which i should follow?
How verilator translates the parameter in verilog code so that i can use them by using defparam
from my SystemC top level.
History
Updated by Wilson Snyder about 3 years ago
- Status changed from New to WillNotFix
There is no way to change Verilog parameters from SystemC. Parameters must be known at elaboration (compile time). No compiled simulator will ever allow this. Sorry.
Either make the parameters into wires (if they don't change the width of anything), or make multiple compilations with the module each way you need, and select which you instantiate at run time.
If you want the other direction (see Verilog params in SystemC) then /*verilator public*/ attached to the parameter will do this.
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