Issue #256: vhier support of "myreg <= #`FFDLY 'b0;" Verilog notation - Verilog-Perl - Veripool

Issue #256

vhier support of "myreg <= #`FFDLY 'b0;" Verilog notation

Added by Evgeni Stavinov about 3 years ago. Updated about 1 year ago.

Status:

Assigned

Start date:

05/27/2010

Priority:

Normal

Due date:

Assignee:

Wilson Snyder

% Done:

Category:

Target version:

Description

When running vhier on the code with "myreg <= #`FFDLY 'b0;" Verilog notation, I'm getting the following error:

%Error: /mypath/myfile.v:some_line: syntax error, unexpected ';', expecting CLASS-IDENTIFIER or COVERGROUP-IDENTIFIER or TYPE-IDENTIFIER

The code is:

`define FFDLY 100 always @(posedge clk) begin if (reset) begin myreg1 <= #`FFDLY 7'd0; myreg2 <= #`FFDLY 'b0; ....

No other synthesis and sim tool has a problem with that.

History

#1 Updated by Wilson Snyder about 3 years ago

Status changed from New to Assigned
Assignee set to Wilson Snyder

Wow, you're right.

Looking at the spec, the leading hash means "# 1 'b0" must be interpreted as "# 1" then "'b0" while if the leading "#" wasn't there it would be "1'b0". Ditto any other place a integer can appear "next to" a based number. Thus numbers can't be determined standalone without knowing the context. That's a really nasty thing for any language standard to require.

Let me think about this. Meantime, use #(`FFDLY) or #`FFDLY 1'b0.

#2 Updated by Wilson Snyder over 1 year ago

This is a duplicate of bug406 (for verilator).

#3 Updated by Wilson Snyder about 1 year ago

See also bug507 (which was hacked around so now resolved).

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