Verilog-mode

It would be nice to have the autoformat/indent feature also for verilog 2001 module headers.

e.g.:

module test_module(
  input wire [1:0]      pin1,
  input wire      pin2,
  input wire [1:0]      pin3,
  input wire        pin4,
  output wire     pin5,
  output wire [10:0] pin6,
  output reg     pin7,
  output reg  [1:0]     pin8
  );

to something like:

module test_module(
  input  wire [1:0]  pin1,
  input  wire        pin2,
  input  wire [1:0]  pin3,
  input  wire        pin4,
  output wire        pin5,
  output wire [10:0] pin6,
  output reg         pin7,
  output reg  [1:0]  pin8
  );

Best regards, Joachim