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Issue #265

Problem with clocks after commit e57d0047184

Added by Byron Bradley almost 2 years ago. Updated over 1 year ago.

Status:Closed Start date:06/14/2010
Priority:Normal Due date:
Assignee:Wilson Snyder % Done:

0%
Category:WrongRuntimeResult
Target version:-

Description

Commit e57d0047184 has caused one of our blocks to start failing all of the tests, reverting this commit makes them pass again. The problem seems to be related to clocks with multiple bits, i.e. our the top module contains: 
input   logic [1:0] clk
and only one bit is being passed into a module: 
someModule #(1) SOME_MODULE (.clk(clk[0]), ...)

History

#1
Updated by Wilson Snyder almost 2 years ago

  • Status changed from New to Assigned
  • Assignee set to Wilson Snyder

I added the t/t_clk_2in_vec.pl to look for this bug, but it didn't turn up. Can you give more details of what the primary input looks like and what loads are on the bussed clock?

#2
Updated by Wilson Snyder almost 2 years ago

  • Status changed from Assigned to AskedReporter

BTW this is still waiting on a testcase.

#3
Updated by Wilson Snyder over 1 year ago

Please reopen with a test case if still failing, thanks.

#4
Updated by Wilson Snyder over 1 year ago

  • Status changed from AskedReporter to Closed

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