Verilog-Perl

It already should ignore `protected. Can you send a small example? (Truncate away, since the data shouldn't matter.)

I've reduced it down to 2 files. I run the following command: vhier -sv --nomissing --top-module nios --module-files *.v

The problem is the auto-generated nios.v file which includes multiple modules and a testbench at the end of the file. Just before the testbench module, there were a lot of include statements (one of which includes np0_cpu.v and it happens to be encrypted).

This happens to be in a section of code delimited by "// synthesis translate_off" and "// synthesis translate_on" and in this case could be ignored by vhier.

Hope this help.

Thanks, Tim

This code simply `includes a file which contains binary text. This isn't legal according to spec, it needs to have a `protected and `endprotected around it.

I don't understand how any simulator would understand what to do with it; if you find the standard that defines how to deal with this, let me know. Meanwhile I'd suggest adding a `ifdef SYNTHESIS `endif around it.

BTW I deleted the attachments from the site because they were copyrighted.

Not a bug here.