Verilog-mode

// This is an example file to show the indentation errors I see with
// the verilog-mode.

// The assumption is that this file will be included into another
// file defining a module.

initial begin
   int unsigned count = 0;
   int value; // ERROR #1: value should align with count
   string source_str;
end

   task begin_trans // ERROR #2 task should align with end
     (input int h_stream ///<[in ] Handle of the stream to use
      );
   endtask : begin_trans

   //////////////////////////////////////////////////////////////////////
       // ERROR #3 Doxygen inline comment should not cause this indent