Verilog-Perl

Top level implicit wires are discarded. Adding a 'wire a;' declaration fixes it.

module sink (input in, output out);

endmodule

module buffer (input in, output out);

wire out = in;

endmodule

module source( input in, output out);

endmodule;

module wrap( input sink_in, buffer_in, source_in, 
             output sink_out, buffer_out, source_out );

source Isource (.in(source_in), .out(source_out));
buffer Ibuffer (.in(buffer_in), .out(buffer_out));
sink   Isink    (top_.in(top_sink_in),  .out(top_sink_out));

endmodule;

module test;

wire top_sink_in = 1;

// source -> buffer -> sink
wrap Iwrap (
    .sink_in(top_buffer_out),
    .buffer_in(top_source_out),
    .source_in(top_buffer_out),
    .sink_out(top_sink_out),
    .buffer_out(top_buffer_out),
    .source_out(top_source_out)
);

endmodule

use Verilog::Netlist;

$Netlist  = shift @ARGV || 'test.v';
$Top      = shift @ARGV || 'test';

print "Loading $Netlist...\n";
my $N = new Verilog::Netlist(
    implicit_wires_ok=>1,
);
$N->read_file (filename=>$Netlist);
$N->link();
$N->lint();
$N->exit_if_error();
print "Done.\n";

my $root = $N->find_module($Top) or die "Can't find $Top in $Netlist!\n";

print "Nets : \n";
foreach my $n ($root->nets_sorted) {
    print $n,' ',$n->name,"\n";
}

print "Cell Pins :\n";
foreach my $c ($root->cells_sorted) {
    print $c->submodname,' ',$c->name,"\n";
    foreach my $p ($c->pins) {
        print "  ",$p->name," ",$p->netname,"=",$p->net,"\n";
    }
}

Loading test.v...
Done.
Nets : 
Verilog::Netlist::Net=ARRAY(0xb18960) top_source_in
Cell Pins :
wrap Iwrap
  source_in top_buffer_out=
  sink_in top_buffer_out=
  sink_out top_sink_out=
  source_out top_source_out=
  buffer_out top_buffer_out=
  buffer_in top_source_out=

wire top_sink_out;
wire top_buffer_out;
wire top_buffer_in;
wire top_source_in;
wire top_source_out;

and you get this

Loading test2.v...
Done.
Nets : 
Verilog::Netlist::Net=ARRAY(0xb19680) top_buffer_in
Verilog::Netlist::Net=ARRAY(0xb194d0) top_buffer_out
Verilog::Netlist::Net=ARRAY(0xb18ba0) top_sink_in
Verilog::Netlist::Net=ARRAY(0xb18d50) top_sink_out
Verilog::Netlist::Net=ARRAY(0xb1a590) top_source_in
Verilog::Netlist::Net=ARRAY(0xb1a740) top_source_out
Cell Pins :
wrap Iwrap
  source_in top_buffer_out=Verilog::Netlist::Net=ARRAY(0xb194d0)
  sink_in top_sink_in=Verilog::Netlist::Net=ARRAY(0xb18ba0)
  sink_out top_sink_out=Verilog::Netlist::Net=ARRAY(0xb18d50)
  source_out top_source_out=Verilog::Netlist::Net=ARRAY(0xb1a740)
  buffer_out top_buffer_out=Verilog::Netlist::Net=ARRAY(0xb194d0)
  buffer_in top_sink_out=Verilog::Netlist::Net=ARRAY(0xb18d50)