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Issue #279

SystemVerilog Constraint auto-indentation

Added by Kev Pet over 1 year ago. Updated over 1 year ago.

Status:Assigned Start date:08/18/2010
Priority:Normal Due date:
Assignee:Michael McNamara % Done:

0%

Category:Indents
Target version:-

Description

When a constraint block contains foreach or if statements, auto-indent does not work
constraint PortCfg::SubportSpeedCnstr
  {
   solve subportCnt before subportSpeedArr;
   subportSpeedArr.size == subportCnt;

   foreach(subportSpeedArr[i])
   {
    if(subportMode == SP10X)
    {
   subportSpeedArr[i] inside {SP1G,SP10G};
}
    }
   }

History

Updated by Wilson Snyder over 1 year ago

  • Category set to Indents
  • Status changed from New to Assigned
  • Assignee set to Michael McNamara

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