Verilator

In some cases, Verilator's lint misses an incorrectly-typed assignment, and instead of producing an error, causes the C++ built to fail. A snippet demonstrating this is as follows:

        reg [31:0] cache_data_hi [127:0 /* {line,word} */];
        reg [31:0] cache_data_lo [127:0 /* {line,word} */];

        wire [31:0] curdata_hi_3a = cache_data_hi[{idx_3a,didx_word_3a}];
        wire [31:0] curdata_lo_3a = cache_data_lo[{idx_3a,didx_word_3a}];
        always @(*) begin
                dc__rw_wait_3a = (dc__rd_req_3a && !cache_hit_3a) || (dc__wr_req_3a && !fsab_credit_avail);
                dc__rd_data_3a = dc__addr_3a[2] ? cache_data_hi : cache_data_lo;
                if (!dc__rw_wait_3a && dc__rd_req_3a)
                        $display("DCACHE: READ COMPLETE: Addr %08x, data %08x", dc__addr_3a, dc__rd_data_3a);
        end

The dc__rd_data_3a is the bogus line; it should have been curdata_{hi,lo}_3a, but that should have been an error certainly. When I try to build the output produced:

joshua@escape:~/school/18-545/virtexsquared/runs/test/sim/obj_dir$ make -f VDCache.mk
g++  -I. -MMD -I/usr/local/share/verilator/include -DVL_PRINTF=printf -DVM_TRACE=0 -DVM_COVERAGE=0       -c -o VDCache__ALLcls.o VDCache__ALLcls.cpp
In file included from VDCache__ALLcls.cpp:2:
VDCache.cpp: In static member function 'static void VDCache::_settle__TOP__3(VDCache__Syms*)':
VDCache.cpp:334: error: invalid conversion from 'IData*' to 'IData'
VDCache.cpp: In static member function 'static void VDCache::_combo__TOP__4(VDCache__Syms*)':
VDCache.cpp:357: error: invalid conversion from 'IData*' to 'IData'
make: *** [VDCache__ALLcls.o] Error 1

A full Verilog module that will cause Verilator to barf in this way is at http://nyus.joshuawise.com/DCache.bug.v .