Issue #286: Identation of classes inside package in SystemVerilog - Verilog-mode - Veripool

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Issue #286

Status:

New

Start date:

09/27/2010

Priority:

Low

Due date:

Assignee:

% Done:

Category:

Indents

Target version:

Description

Hi, Classes are not indented when declared in a package.

package toto; class titi; endclass endpackage

Should rather be, in my opinion:

package toto; class titi; endclass endpackage

Thanks, Pierre

I'm using version 639 of Verilog mode.

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