Verilog-Perl

Some Verilog RTL we received from a vendor (i.e. we can't easily change it) uses an ifdef to control the instantiation of a module. The macro name in the ifdef is the same as the module name. Something like this simplified example:

module top;
`define MYMOD

`ifdef MYMOD
  MYMOD uMYMOD();
`endif

endmodule

MYMOD.v exists in a subdirectory (subdir/MYMOD.v). Vhier cannot locate it when I use -y to point to the subdir:

vhier --module-files top.v -y subdir +libext+.v
%Error: top.v:7: Cannot find MYMOD
%Error: top.v:7: Module/Program/Interface reference not found: MYMOD
Exiting due to errors

vhier --module-files top.v  subdir/MYMOD.v
   top.v
    subdir/MYMOD.v

The culprit appears to be this bit of code in Netlist.pm:

sub remove_defines {
    my $self = shift;
    my $sym = shift;
    # This function is HOT
    # We only remove defines one level deep, for historical reasons.
    # We don't require a ` as SystemC also uses this function and doesn't use `.
    (my $xsym = $sym) =~ s/^\`//;
    my $val = $self->defvalue_nowarn($xsym);  #Undef if not found
    $sym = $val if defined $val;
    return $sym;
}

In top.v, the module name MYMOD does not have a leading ` so it shouldn't be treated as a macro. But it is expanded to the macro's value (the empty string) which prevents MYMOD.v from being found.