Verilator

The code within the first always loop below will be executed differently depending on the clk signal being observed in the second always loop. For instance, when the clk is quiet, the first always loop will be executed a few times (it should really only happen once) with static in1, in2, in3 values, and many times when the clk signal starts toggling.

module transition_statement_bug(sig1, sig2, sig3, clk);

input sig1;
input sig2;
input sig3;
input clk;
reg state_val;
reg flag;

initial begin
   state_val = 1'b0;
   flag = 1'b0;
end

always @(sig1 or sig2 or sig3) begin
   case({sig1,sig2,sig3})
      3'b111 : begin
          flag = 1'b0;
          $display("---- Flag is zero %d %d %d",sig1,sig2,sig3);
      end
      default : begin
          if(flag == 0) begin
             flag = 1'b1;
             $display("---- Flag is one %d %d %d",sig1,sig2,sig3);
          end
      end
   endcase
end

always @(posedge clk) begin
   state_val <= (state_val == 1'b0) ? 1'b1 : 1'b0;
end

endmodule
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