Verilog-mode

Hi,
It seems to me there are at least 2 problems with the .* for interfaces. E.g.

interface intf1;
  logic a;
  logic b;
  modport mp1 (input a, output b);
endinterface

interface intf2 (intf1.mp1 c);
  logic e;
endinterface

module top;
  intf1 c(.*);
  intf2 f(.*);
endmodule

First, some comments are left out when saving the file after C-c C-a (this is cosmetics, but is a little annoying).
Second, I'm not sure the internal declarations (i.e. not the port declarations) should be in the interface connection. I think it should not since these are not interface ports. When I try to compile, it produces compilation error. E.g. Signals 'a' and 'b' for c interface instantiation in 'top' should not be in the interface connection, same for signal 'e' for 'f' interface instantiation in 'top'.
Thanks,
Pierre