[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  Schedule::Load
  SVN::S4
  Synopsys-modes
  SystemPerl
  Verilog-Pli
  Voneline
  Vregs
General Info
  Papers

Issue #321

lint does not complain about double port usage

Added by Christian Leber over 1 year ago. Updated over 1 year ago.

Status:Closed Start date:01/29/2011
Priority:Low Due date:
Assignee:Wilson Snyder % Done:

0%

Category:Lint
Target version:-

Description

Hello,

we found a pretty simple problem in the linter, when people are not using other tools to stumble upon such problems it may stay undetected in the C++ simulation.

As you can see it does not complain about the instantiation of sub despite the i port is used 2 times, furthermore it also does not complain about the extra , at the end.

Btw.: verilator linting is a great help for quick repo sanity checks, thanks! Christian Leber

sub.v (75 Bytes) Christian Leber, 01/29/2011 06:04 pm

top.v (120 Bytes) Christian Leber, 01/29/2011 06:04 pm

History

Updated by Wilson Snyder over 1 year ago

  • Status changed from New to Feature
  • Assignee set to Wilson Snyder

How could that happen? Don't tell me you're still writing ports by hand instead of using "AUTOINST"? :)

BTW, it IS legal to have the trailing comma in some cases, it indicates an empty port connection when doing by order connectivity. Thus verilator simply dropped them.

Anyhow fixed in git for 3.811.

Updated by Wilson Snyder over 1 year ago

  • Status changed from Feature to Resolved

Updated by Wilson Snyder over 1 year ago

  • Status changed from Resolved to Closed

In 3.811.

Also available in: Atom