Verilog-mode

Hello:

This is not an issue, but a question or RFE.

Regarding your description below: When using multiple layers of parenthesis, is there a way I can use (or some other variable) to replace any of those regular expression matches. For e.g. Say [1] will result in \([0-9]+\) match.

"If you use multiple layers of parenthesis, "test\([^0-9]+\)_\([0-9]+\)" would replace with non-number characters after test and before _, whereas "\(test\([a-z]+\)_\([0-9]+\)\)" would replace with the entire match."