Verilog-mode

The constraint indentation for SV is not correct for verilog-mode version 648 to 662. Here is an example:

class myclass; 
   constraint c {
                 foreach (items[i]) {
                                     if (write) {
      items[i].op_code == WRITE;
   } else if (read) {
      items[i].op_code == READ;      
   }
                                     }
                 }
endclass

Matching C, I would have expected:

class myclass; 
   constraint c {
     foreach (items[i]) {
       if (write) {
         items[i].op_code == WRITE;
       } else if (read) {
         items[i].op_code == READ;      
       }
     }
   }
endclass

Or, I could see producing something like the below... since some people prefer the code to line up with the {}

class myclass; 
   constraint c {
                 foreach (items[i]) {
                                     if (write) {
                                                 items[i].op_code == WRITE;
                                                } else if (read) {
                                                 items[i].op_code == READ;      
                                                }
                                     }
                 }
endclass

If I don't like the previous output lining up with {}, I can place the {}'s on their own line... but I get this:

class myclass; 
   constraint c 
     {
      foreach (items[i]) 
      {
       if (write) 
       {
      items[i].op_code == WRITE;
   } 
       else if (read) 
       {
      items[i].op_code == READ;      
   }
       }
      }
endclass