verilog-mode infinite loops with malformed input
|Assignee:||Wilson Snyder||% Done:|
One of my students (Andrew Drake) just sent me this (minimized) example code, which causes verilog-mode to infinitely loop.
module aaa(); always @(a) begin if (a) begin /*AUTORESET*/ end endmodule module bbb(); always @(*) begin end endmodule
He mentioned that his development cycle involves typing a lot of code, and instinctively pressing his auto keyboard shortcut. He was very confused when verilog-mode hung... He notes that there is an 'end' missing above, which he believes to be related.