Verilator

Vectored bufif1 primitive does not compile as expected. I attached two exampled showing two issues. The code on which the examples were based works properly in Icarus Verilog and ncsim.

The first issue is a WIDTH warning that should not be reported:

$ verilator --lint-only tristate_vector.v %Warning-WIDTH: tristate_vector.v:9: Logical Operator COND expects 1 bit on the Conditional Expression, but Conditional Expression's VARREF 'drv_e' generates 4 bits. %Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: tristate_vector.v:9: Operator COND expects 4 bits on the Conditional False, but Conditional False's CONST '1'bz' generates 1 bits. %Error: Exiting due to 2 warning(s) %Error: Command Failed verilator_bin --lint-only tristate_vector.v

The other issue is a parser error:

verilator --lint-only tristate_list.v %Error: tristate_list.v:12: syntax error, unexpected '{', expecting IDENTIFIER %Error: Exiting due to 1 warning(s) %Error: Command Failed verilator_bin --lint-only tristate_list.v