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Issue #330
Identation after always* construct inside named block
| Status: | New | Start date: | 03/08/2011 | |
|---|---|---|---|---|
| Priority: | Normal | Due date: | ||
| Assignee: | Michael McNamara | % Done: | 0% |
|
| Category: | Autos | |||
| Target version: | - |
Description
Hi,
It looks like indentation is wrong after the first always_ff (I think this is also true for other types of always) inside a named block (I'm using version 665). E.g.:
It looks like indentation is wrong after the first always_ff (I think this is also true for other types of always) inside a named block (I'm using version 665). E.g.:
module testcase;
begin : block
logic s1, s2;
wire w1 = '1;
wire w2 = '0;
always_ff @(clk) s1 <= w1;
always_ff @(clk) s2 <= s1; // wrong indentation
end // wrong indentation
endmodule
Thanks,
Pierre
History
Updated by Pierre-David Pfister about 1 year ago
This is still true in 667, Pierre.
Updated by Wilson Snyder about 1 year ago
- Category set to Autos
- Assignee set to Michael McNamara
Not that we shouldn't necessarily indent them, but "bare" begin/end blocks are a Verilog 2001 feature that were deprecated in SystemVerilog 2005. Note if you throw it in a "generate"/"endgenerate" it works correctly.
Anyhow, up to Mac.
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