Verilog-mode

If you use parameters calculated from other parameters in port widths, they appear at the instantiation even if you have verilog-auto-inst-param-value set.

Below is an example where b is just a+5, however, more commonly it will be b=func(a) where func might be log or something like that.

module foo();

  bar #(.a(6)) ibar(/*autoinst*/
            // Inputs
            .in_wire0        (in_wire0[5:0]),
            .in_wire1        (in_wire1[b-1:0]));

endmodule

module bar
  #(parameter 
    a=3,
    b=a+5
    )
  (
   input [a-1:0] in_wire0;
   input [b-1:0] in_wire1;
   );

endmodule