Issue #335: type casting does not work - Verilator - Veripool

Issue #335

Status:

Closed

Start date:

03/16/2011

Priority:

Normal

Due date:

Assignee:

% Done:

Category:

Unsupported

Target version:

Description

Example:

`define MC_WIDTH 32 typedef logic [`MC_WIDTH-1:0] mc_t;

module t( output mc_t o, input mc_t i );

always_comb begin
   o = mc_t'(1);
end

endmodule // t

Modelsim compiles just fine but verilator does not:

%Error: tmp.v:8: syntax error, unexpected TYPE-IDENTIFIER %Error: Exiting due to 1 warning(s)

Fixed in git for 3.812.

BTW only simple scalar types are supported, no arrays etc. I suspect there will be later improvements needed here.

In 3.812.

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