Verilator

Verilog code:

typedef enum logic [1:0] { BIT0 = 2'd0, BIT1 = 2'd1, BIT2 = 2'd2 } bit_t;

module test ( );

logic [2:0] vector;
logic       bit0;
logic       bit1;
logic       bit2;

assign bit0 = vector[BIT0];
assign bit1 = vector[BIT1];
assign bit2 = vector[BIT2];

endmodule // test

Verilator output:

verilator --cc test.v %Error: Internal Error: test.v:15: ../V3Width.cpp:664: EnumItem not under a Enum %Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance. %Error: Command Failed verilator_bin --cc test.v

Modelsim compiles without problem.