Verilator

It seems that when assigning constant expressions to a signal, Verilator expects the LSH to be as wide as the widest parameter on the RHS, rather than the result of the expression. For example, when compiling the following code:

`define NUM 32

module test (output logic [4:0] counter, input logic clk, input logic rst); endmodule // test

always_ff @(posedge clk) begin
   if (rst)
     counter <= `NUM - 1;
   else
     counter <= counter - 1;
end

gets the following warning:

%Warning-WIDTH: test.v:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 or 6 bits. %Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to 1 warning(s) %Error: Command Failed verilator_bin --cc test.v --top-module test

This is while `NUM-1 fits exactly in the 5 bits provided by the LHS signal.