Issue #353: AUTOARG and SV typedef as port - Verilog-mode - Veripool

Issue #353

Status:

Closed

Start date:

05/17/2011

Priority:

Normal

Due date:

Assignee:

% Done:

Category:

Autos

Target version:

Description

Hi,

I run in trouble when trying to use the following typedef as port:

typedef struct packed {
    flit_type_t ftype;
    bit[31:0] content;
} flit_t;

And in the module:

module mymodule(/*AUTOARG*/);

   input flit_t flit;

When applying autos I get

module mymodule(/*AUTOARG*/
   flit_t, flit
   );
   input flit_t flit;

It seems that parsing does not work properly. I use the latest release.

Thanks and regards, Stefan

You need to set verilog-typedef-regexp. Please see the FAQ for the different ways to do this.

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