Verilator

I reduced the problem case to the following test (verilator still hangs up and leaks memory):

`define CLK2Q
`define MC_FFF_WIDTH  40
`define NUM_PORTS     2

typedef logic [$clog2(32+1)-1:0]  eee_t;
typedef logic [`MC_FFF_WIDTH-1:0] mc_fff_t;
typedef logic [$bits(eee_t):0]    mc_ggg_t;

module bbb #( parameter DEPTH=2 )
   (
    output mc_ggg_t                    ggg_out[`NUM_PORTS-1:0],
    output mc_fff_t                    fff_out[`NUM_PORTS-1:0],
    output logic [$clog2(DEPTH+1)-1:0] cnt_out[`NUM_PORTS-1:0],

    // Mmmueue
    input logic                        mmm0_in[`NUM_PORTS-1:0],
    input mc_ggg_t                     id0_in [`NUM_PORTS-1:0],
    input mc_fff_t                     fff0_in[`NUM_PORTS-1:0],
    input logic                        mmm1_in[`NUM_PORTS-1:0],
    input mc_ggg_t                     id1_in [`NUM_PORTS-1:0],
    input mc_fff_t                     fff1_in[`NUM_PORTS-1:0],

    // Nnnueue
    input logic                        nnn_in [`NUM_PORTS-1:0],

    // General
    input logic                        clk,
    input logic                        rst
    );

   localparam CNT_WIDTH = $clog2(DEPTH+1);

   mc_ggg_t              id [DEPTH-1:0];
   mc_fff_t              fff[DEPTH-1:0];
   logic [CNT_WIDTH-1:0] cnt[`NUM_PORTS-1:0],
                         kkk[`NUM_PORTS-1:0],
                         lll[`NUM_PORTS-1:0];
   mc_fff_t              kkk_fff[`NUM_PORTS-1:0];
   logic                 ppp[`NUM_PORTS-1:0];

   genvar                i;

   generate
      for( i=0; i<`NUM_PORTS; i++ ) begin: PPP
         assign ppp[i] = (cnt[i] == 0) || (nnn_in[i]  && (cnt[i] == 1));
         assign ggg_out      [i] = kkk    [i];
         assign fff_out      [i] = kkk_fff[i];
         assign cnt_out      [i] = cnt    [i];
      end
   endgenerate

   generate
      for( i=0; i<`NUM_PORTS; i++ ) begin: QUEUE_LOGIC
         always_ff @(posedge clk) begin
            if( rst ) begin
               kkk[i] <= `CLK2Q 0;
            end
            else begin
               if( mmm0_in[i] && ppp[i] ) begin
                  kkk    [i] <= `CLK2Q id0_in [i];
                  kkk_fff[i] <= `CLK2Q fff0_in[i];
               end
               else if( mmm1_in[i] && ppp[i] ) begin
                  kkk    [i] <= `CLK2Q id1_in [i];
                  kkk_fff[i] <= `CLK2Q fff1_in[i];
               end
               else if( nnn_in && (cnt > 1) ) begin
                  kkk    [i] <= `CLK2Q id [kkk[i]];
                  kkk_fff[i] <= `CLK2Q fff[kkk[i]];
               end
            end // else: !if( rst )
         end // always_ff @

         always_ff @(posedge clk) begin
            if( rst ) begin
               lll[i] <= `CLK2Q 0;
            end
            else begin
               if( mmm1_in[i] ) begin
                  lll[i] <= `CLK2Q id1_in[i];
               end
               else if( mmm0_in[i] ) begin
                  lll[i] <= `CLK2Q id0_in[i];
               end
            end // else: !if( rst )
         end // always_ff @

         always_ff @(posedge clk) begin
            if( rst ) begin
               cnt[i] <= `CLK2Q 0;
            end
            else begin
               if( mmm0_in[i] && mmm1_in[i] && !nnn_in[i] ) begin
                  cnt[i] <= `CLK2Q cnt[i] + 'd2;
               end
               else if( ( mmm0_in[i] && !mmm1_in[i] && !nnn_in[i]) ||
                        (!mmm0_in[i] &&  mmm1_in[i] && !nnn_in[i]) ||
                        ( mmm0_in[i] &&  mmm1_in[i] &&  nnn_in[i]) ) begin
                  cnt[i] <= `CLK2Q cnt[i] + 'd1;
               end
               else if( !mmm0_in[i] && !mmm1_in[i] && nnn_in[i] ) begin
                  assert( cnt[i] > 0 );
                  cnt[i] <= `CLK2Q cnt[i] - 'd1;
               end
            end // else: !if( rst )
         end // always_ff @
      end // block: QUEUE_LOGIC
   endgenerate

   always_ff @(posedge clk) begin
      if( !rst ) begin
         for( i=0; i<`NUM_PORTS; i++ ) begin
            if( mmm0_in[i] && mmm1_in[i] ) begin
               if( !ppp[i] ) begin
                  id [lll[i]] <= `CLK2Q id0_in [i];
                  fff[lll[i]] <= `CLK2Q fff0_in[i];
               end
               id [id0_in[i]]  <= `CLK2Q id1_in [i];
               fff[id0_in[i]]  <= `CLK2Q fff1_in[i];
            end

            else if( mmm1_in[i] && !ppp[i] ) begin
               id [lll[i]] <= `CLK2Q id1_in [i];
               fff[lll[i]] <= `CLK2Q fff1_in[i];
            end

            else if( mmm0_in && !ppp ) begin
               id [lll[i]] <= `CLK2Q id0_in [i];
               fff[lll[i]] <= `CLK2Q fff0_in[i];
            end
         end // for ( i=0; i<`NUM_PORTS; i++ )
      end // if ( !rst )
   end // always_ff @

endmodule

module aaa #( parameter NUM_DDDS=1 )
   (

    input eee_t                     iii_req_eee_in,
    input eee_t                     jjj_req_eee_in,

    // General
    input logic                     clk,
    input logic                     rst
    );

   localparam DDD_NUM_WIDTH    = $clog2(2*NUM_DDDS+1);

   mc_fff_t                     iii_hhh_ooo_fff,
                                jjj_hhh_ooo_fff;

   logic [DDD_NUM_WIDTH-1:0]    hp_hhh_cnt;
   mc_ggg_t                     hp_hhh_kkk;
   mc_fff_t                     hp_hhh_ooo_fff;

   logic [DDD_NUM_WIDTH-1:0]    hhh_cnt;
   mc_ggg_t                     hhh_kkk;
   mc_fff_t                     hhh_ooo_fff;

   logic                        iii_hp_hhh,
                                iii_hhh,
                                iii_other,
                                jjj_hp_hhh,
                                jjj_hhh,
                                jjj_other;

   logic                        mmm_iii_hp_hhh,
                                mmm_jjj_hp_hhh,
                                nnn_hp_hhh,
                                mmm_iii_hhh,
                                mmm_jjj_hhh,
                                nnn_hhh;

  bbb #(.DEPTH(2*NUM_DDDS)) ccc( .ggg_out ({hp_hhh_kkk,             hhh_kkk}),
                                 .fff_out ({hp_hhh_ooo_fff,         hhh_ooo_fff}),
                                 .cnt_out ({hp_hhh_cnt,             hhh_cnt}),
                                 .nnn_in  ({nnn_hp_hhh,             nnn_hhh}),
                                 .mmm0_in ({mmm_jjj_hp_hhh,         mmm_jjj_hhh}),
                                 .id0_in  ({{1'b1, jjj_req_eee_in}, {1'b1, jjj_req_eee_in}}),
                                 .fff0_in ({jjj_hhh_ooo_fff,        jjj_hhh_ooo_fff}),
                                 .mmm1_in ({mmm_iii_hp_hhh,         mmm_iii_hhh}),
                                 .id1_in  ({{1'b0, iii_req_eee_in}, {1'b0, iii_req_eee_in}}),
                                 .fff1_in({iii_hhh_ooo_fff,         iii_hhh_ooo_fff}),
                                 .* );

endmodule

When I run it with --debug, I get the following result:

verilator --cc aaa.v --debug --gdbbt
No stack.
    gdb verilator_bin_dbg --batch --quiet --return-child-result -ex 'run --cc aaa.v --debug --gdbbt' -ex 'set width 0' -ex 'bt'
Starting Verilator 3.813 devel rev verilator_3_812-3-g9a96f62
- V3Options.cpp:352:  export SYSTEMC_ARCH=linux # From sysname 'linux'
- V3File.cpp:188:        --check-times failed: no input obj_dir/Vaaa__verFiles.dat
- V3GraphTest.cpp:356:test: 
- V3ParseImp.cpp:95:  parseFile: aaa
  Preprocessing aaa.v
- V3PreShell.cpp:108:     Reading aaa.v
- V3ParseImp.cpp:141: Lexing aaa.v
- V3LinkCells.cpp:150:Link Module: PACKAGE 0x991860 <e21#> {5} w0  __024unit  L0 [LIB]
- V3LinkCells.cpp:150:Link Module: MODULE 0x9969b0 <e49#> {11} w0  bbb  L0
- V3LinkCells.cpp:150:Link Module: MODULE 0x9c8bc0 <e1604#> {141} w0  aaa  L0
dot -Tps -o ~/a.ps obj_dir/Vaaa_01_linkcells.dot
- V3LinkLevel.cpp:52: modSortByLevel()
- V3Link.cpp:233:     Link Module: MODULE 0x9c8bc0 <e1932> {141} w0  aaa  L2
- V3Link.cpp:233:     Link Module: PACKAGE 0x991860 <e1935> {5} w0  __024unit  L3 [LIB]
- V3Link.cpp:233:     Link Module: MODULE 0x9969b0 <e1936#> {11} w0  bbb  L3
- V3Link.cpp:233:     Link Module: MODULE 0x9c8bc0 <e1932> {141} w0  aaa  L2
- V3Link.cpp:233:     Link Module: PACKAGE 0x991860 <e1935> {5} w0  __024unit  L3 [LIB]
- V3Link.cpp:233:     Link Module: MODULE 0x9969b0 <e1936#> {11} w0  bbb  L3
- V3Link.cpp:233:     Link Module: MODULE 0x9c8bc0 <e1932> {141} w0  aaa  L2
- V3Link.cpp:233:     Link Module: PACKAGE 0x991860 <e1935> {5} w0  __024unit  L3 [LIB]
- V3Link.cpp:233:     Link Module: MODULE 0x9969b0 <e1936#> {11} w0  bbb  L3
- V3LinkDot.cpp:729:  linkDotGuts: 
- V3LinkJump.cpp:239: linkJump: 
- V3Param.cpp:384:    param: 
- V3Unroll.cpp:458:   unrollGen: 
- V3Unroll.cpp:458:   unrollGen: 
- V3Unroll.cpp:458:   unrollGen: 
- V3Unroll.cpp:458:   unrollGen: 
- V3LinkDot.cpp:729:  linkDotGuts: 
- V3Dead.cpp:229:     deadifyAll: 
- V3Width.cpp:1456:   width: 
%Warning-WIDTH: aaa.v:48: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's ARRAYSEL generates 2 bits.
-node: 0xa4e9d0
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: aaa.v:48: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's ARRAYSEL generates 2 bits.
-node: 0xa52b10
%Warning-WIDTH: aaa.v:62: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS's ARRAYSEL generates 7 bits.
-node: 0xa57000
%Warning-WIDTH: aaa.v:66: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS's ARRAYSEL generates 7 bits.
-node: 0xa58db0
%Warning-WIDTH: aaa.v:70: Bit extraction of array[1:0] requires 1 bit index, not 2 bits.
-node: 0xa895d0
- V3Width.cpp:380:        Related node: ARRAYSEL 0xa895d0 <e7517#> {70} w7 [start:0] [length:1]
- V3Width.cpp:381:        Related var: VAR 0x9f4dc0 <e315> {35} w7  id VAR
- V3Width.cpp:382:        Related depth: 0 dtype: ARRAYDTYPE 0x9f4e90 <e314> {35} w7
%Warning-WIDTH: aaa.v:70: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS's ARRAYSEL generates 7 bits.
-node: 0xa5a660
%Warning-WIDTH: aaa.v:71: Bit extraction of array[1:0] requires 1 bit index, not 2 bits.
-node: 0xa87180
- V3Width.cpp:380:        Related node: ARRAYSEL 0xa87180 <e7572#> {71} w40 [start:0] [length:1]
- V3Width.cpp:381:        Related var: VAR 0x9f5490 <e334> {36} w40  fff VAR
- V3Width.cpp:382:        Related depth: 0 dtype: ARRAYDTYPE 0x9f5560 <e333> {36} w40
%Warning-WIDTH: aaa.v:82: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS's ARRAYSEL generates 7 bits.
-node: 0xa5d340
%Warning-WIDTH: aaa.v:85: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS's ARRAYSEL generates 7 bits.
-node: 0xa5e280
%Warning-WIDTH: aaa.v:62: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS's ARRAYSEL generates 7 bits.
-node: 0xa6d3f0
%Warning-WIDTH: aaa.v:66: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS's ARRAYSEL generates 7 bits.
-node: 0xa6f1a0
%Warning-WIDTH: aaa.v:70: Bit extraction of array[1:0] requires 1 bit index, not 2 bits.
-node: 0xa92780
- V3Width.cpp:380:        Related node: ARRAYSEL 0xa92780 <e8278#> {70} w7 [start:0] [length:1]
- V3Width.cpp:381:        Related var: VAR 0x9f4dc0 <e315> {35} w7  id VAR
- V3Width.cpp:382:        Related depth: 0 dtype: ARRAYDTYPE 0x9f4e90 <e314> {35} w7
%Warning-WIDTH: aaa.v:70: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS's ARRAYSEL generates 7 bits.
-node: 0xa70a70
%Warning-WIDTH: aaa.v:71: Bit extraction of array[1:0] requires 1 bit index, not 2 bits.
-node: 0xa93450
- V3Width.cpp:380:        Related node: ARRAYSEL 0xa93450 <e8333#> {71} w40 [start:0] [length:1]
- V3Width.cpp:381:        Related var: VAR 0x9f5490 <e334> {36} w40  fff VAR
- V3Width.cpp:382:        Related depth: 0 dtype: ARRAYDTYPE 0x9f5560 <e333> {36} w40
%Warning-WIDTH: aaa.v:82: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS's ARRAYSEL generates 7 bits.
-node: 0xa73770
%Warning-WIDTH: aaa.v:85: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS's ARRAYSEL generates 7 bits.
-node: 0xa746b0
%Warning-WIDTH: aaa.v:117: Bit extraction of array[1:0] requires 1 bit index, not 2 bits.
-node: 0xa99a20
- V3Width.cpp:380:        Related node: ARRAYSEL 0xa99a20 <e8885#> {117} w7 [start:0] [length:1]
- V3Width.cpp:381:        Related var: VAR 0x9f4dc0 <e315> {35} w7  id VAR
- V3Width.cpp:382:        Related depth: 0 dtype: ARRAYDTYPE 0x9f4e90 <e314> {35} w7
%Warning-WIDTH: aaa.v:118: Bit extraction of array[1:0] requires 1 bit index, not 2 bits.
-node: 0xa9ac40
- V3Width.cpp:380:        Related node: ARRAYSEL 0xa9ac40 <e8948#> {118} w40 [start:0] [length:1]
- V3Width.cpp:381:        Related var: VAR 0x9f5490 <e334> {36} w40  fff VAR
- V3Width.cpp:382:        Related depth: 0 dtype: ARRAYDTYPE 0x9f5560 <e333> {36} w40
%Warning-WIDTH: aaa.v:120: Bit extraction of array[1:0] requires 1 bit index, not 7 bits.
-node: 0xa9c140
- V3Width.cpp:380:        Related node: ARRAYSEL 0xa9c140 <e9032#> {120} w7 [start:0] [length:1]
- V3Width.cpp:381:        Related var: VAR 0x9f4dc0 <e315> {35} w7  id VAR
- V3Width.cpp:382:        Related depth: 0 dtype: ARRAYDTYPE 0x9f4e90 <e314> {35} w7
%Warning-WIDTH: aaa.v:121: Bit extraction of array[1:0] requires 1 bit index, not 7 bits.
-node: 0xa9d100
- V3Width.cpp:380:        Related node: ARRAYSEL 0xa9d100 <e9095#> {121} w40 [start:0] [length:1]
- V3Width.cpp:381:        Related var: VAR 0x9f5490 <e334> {36} w40  fff VAR
- V3Width.cpp:382:        Related depth: 0 dtype: ARRAYDTYPE 0x9f5560 <e333> {36} w40
%Warning-WIDTH: aaa.v:125: Bit extraction of array[1:0] requires 1 bit index, not 2 bits.
-node: 0xa9e510
- V3Width.cpp:380:        Related node: ARRAYSEL 0xa9e510 <e9158#> {125} w7 [start:0] [length:1]
- V3Width.cpp:381:        Related var: VAR 0x9f4dc0 <e315> {35} w7  id VAR
- V3Width.cpp:382:        Related depth: 0 dtype: ARRAYDTYPE 0x9f4e90 <e314> {35} w7
%Warning-WIDTH: aaa.v:126: Bit extraction of array[1:0] requires 1 bit index, not 2 bits.
-node: 0xa9f4d0
- V3Width.cpp:380:        Related node: ARRAYSEL 0xa9f4d0 <e9221#> {126} w40 [start:0] [length:1]
- V3Width.cpp:381:        Related var: VAR 0x9f5490 <e334> {36} w40  fff VAR
- V3Width.cpp:382:        Related depth: 0 dtype: ARRAYDTYPE 0x9f5560 <e333> {36} w40
%Warning-WIDTH: aaa.v:130: Bit extraction of array[1:0] requires 1 bit index, not 2 bits.
-node: 0xaa0490
- V3Width.cpp:380:        Related node: ARRAYSEL 0xaa0490 <e9284#> {130} w7 [start:0] [length:1]
- V3Width.cpp:381:        Related var: VAR 0x9f4dc0 <e315> {35} w7  id VAR
- V3Width.cpp:382:        Related depth: 0 dtype: ARRAYDTYPE 0x9f4e90 <e314> {35} w7
%Warning-WIDTH: aaa.v:131: Bit extraction of array[1:0] requires 1 bit index, not 2 bits.
-node: 0xaa1450
- V3Width.cpp:380:        Related node: ARRAYSEL 0xaa1450 <e9347#> {131} w40 [start:0] [length:1]
- V3Width.cpp:381:        Related var: VAR 0x9f5490 <e334> {36} w40  fff VAR
- V3Width.cpp:382:        Related depth: 0 dtype: ARRAYDTYPE 0x9f5560 <e333> {36} w40
%Warning-WIDTH: aaa.v:180: Output port connection ggg_out expects 7 bits but connection's CONCAT generates 14 bits.
-node: 0x9d0410
%Warning-WIDTH: aaa.v:181: Output port connection fff_out expects 40 bits but connection's CONCAT generates 80 bits.
-node: 0x9d0a20
%Warning-WIDTH: aaa.v:182: Output port connection cnt_out expects 2 bits but connection's CONCAT generates 4 bits.
-node: 0x9d0fc0
%Warning-WIDTH: aaa.v:183: Input port connection nnn_in expects 1 bits but connection's CONCAT generates 2 bits.
-node: 0x9d1590
%Warning-WIDTH: aaa.v:184: Input port connection mmm0_in expects 1 bits but connection's CONCAT generates 2 bits.
-node: 0x9d1ba0
%Warning-WIDTH: aaa.v:185: Input port connection id0_in expects 7 bits but connection's CONCAT generates 14 bits.
-node: 0x9d26a0
%Warning-WIDTH: aaa.v:186: Input port connection fff0_in expects 40 bits but connection's CONCAT generates 80 bits.
-node: 0x9d2c80
%Warning-WIDTH: aaa.v:187: Input port connection mmm1_in expects 1 bits but connection's CONCAT generates 2 bits.
-node: 0x9d3260
%Warning-WIDTH: aaa.v:188: Input port connection id1_in expects 7 bits but connection's CONCAT generates 14 bits.
-node: 0x9d3d60
%Warning-WIDTH: aaa.v:189: Input port connection fff1_in expects 40 bits but connection's CONCAT generates 80 bits.
-node: 0x9d4340
- V3Signed.cpp:438:   signedAll: 
- V3Width.cpp:1479:   widthCommit: 
- V3Const.cpp:1988:   constifyAllLive: 
- V3Undriven.cpp:320: undrivenAll: 
- V3AssertPre.cpp:154:assertPreAll: 
- V3Assert.cpp:307:   assertAll: 
- V3LinkLevel.cpp:87: wrapTop: 
- V3Const.cpp:1967:   constifyAllLint: 
- V3Tristate.cpp:732: inoutAll: 
- V3Inst.cpp:314:     dearrayAll: 
- V3Tristate.cpp:727: tristateAll: 
- V3Begin.cpp:190:    debeginAll: 
- V3Unknown.cpp:466:  unknownAll: 
- V3Inline.cpp:447:   inlineAll: 
- V3LinkDot.cpp:729:  linkDotGuts: 
- V3Const.cpp:1995:   constifyAll: 
- V3Dead.cpp:229:     deadifyAll: 
- V3Inst.cpp:309:     instAll: 
- V3Const.cpp:1995:   constifyAll: 
- V3Scope.cpp:354:    scopeAll: 
- V3LinkDot.cpp:729:  linkDotGuts: 
- V3Const.cpp:1995:   constifyAll: 
- V3Dead.cpp:229:     deadifyAll: 
- V3Task.cpp:1212:    taskAll: 
dot -Tps -o ~/a.ps obj_dir/Vaaa_22_task_call.dot
- V3Name.cpp:139:     nameAll: 
- V3Unroll.cpp:453:   unrollAll: 
- V3Slice.cpp:499:    sliceAll: 
%Error: aaa.v:180: Unsupported: Assignment between packed arrays of different dimensions
-node: 0xb7bd60
%Error: aaa.v:181: Unsupported: Assignment between packed arrays of different dimensions
-node: 0xb7c6f0
%Error: aaa.v:182: Unsupported: Assignment between packed arrays of different dimensions
-node: 0xb7d080
%Error: aaa.v:185: Unsupported: Assignment between packed arrays of different dimensions
-node: 0xb7da50
%Error: aaa.v:188: Unsupported: Assignment between packed arrays of different dimensions
-node: 0xb7dfc0

Program received signal SIGINT, Interrupt.
0x00000000004408dd in std::vector<unsigned int, std::allocator<unsigned int> >::begin (this=0x602bf5c0)
    at /usr/lib/gcc/x86_64-redhat-linux/4.4.5/../../../../include/c++/4.4.5/bits/stl_vector.h:435
435          { return const_iterator(this->_M_impl._M_start); }
#0  0x00000000004408dd in std::vector<unsigned int, std::allocator<unsigned int> >::begin (this=0x602bf5c0) at /usr/lib/gcc/x86_64-redhat-linux/4.4.5/../../../../include/c++/4.4.5/bits/stl_vector.h:435
#1  0x000000000044033a in std::vector<unsigned int, std::allocator<unsigned int> >::vector (this=0x602bf8b0, __x=std::vector of length 2, capacity 2 = {...}) at /usr/lib/gcc/x86_64-redhat-linux/4.4.5/../../../../include/c++/4.4.5/bits/stl_vector.h:243
#2  0x00000000004258ff in V3Number::V3Number (this=0x602bf8a0) at ../V3Number.h:33
#3  0x0000000000425fd5 in AstConst::AstConst (this=0x602bf7f0) at ../V3AstNodes.h:44
#4  0x0000000000426030 in AstConst::clone (this=0x602bf500) at ../V3AstNodes.h:71
#5  0x0000000000480f16 in AstNode::cloneTreeIter (this=0x602bf500) at ../V3Ast.cpp:629
#6  0x000000000048101d in AstNode::cloneTreeIterList (this=0x602bf500) at ../V3Ast.cpp:646
#7  0x0000000000480f4c in AstNode::cloneTreeIter (this=0x602bf350) at ../V3Ast.cpp:631
#8  0x000000000048110e in AstNode::cloneTree (this=0x602bf350, cloneNextLink=false) at ../V3Ast.cpp:666
#9  0x00000000005d1733 in AstArraySel::cloneTree (this=0x602bf350, cloneNext=false) at ../V3AstNodes.h:424
#10 0x00000000005d2f23 in SliceVisitor::visit (this=0x7fffffffd670, nodep=0x602bf350) at ../V3Slice.cpp:341
#11 0x0000000000489f83 in AstArraySel::accept (this=0x602bf350, v=..., vup=0x0) at ../V3AstNodes.h:424
#12 0x00000000004816fb in AstNode::iterateAndNext (this=0xb81ad0, v=..., vup=0x0) at ../V3Ast.cpp:772
#13 0x000000000048154d in AstNode::iterateChildren (this=0xb81a10, v=..., vup=0x0) at ../V3Ast.cpp:753
#14 0x00000000005d39de in SliceVisitor::visit (this=0x7fffffffd670, nodep=0xb81a10) at ../V3Slice.cpp:482
#15 0x0000000000470de7 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0xb81a10, vup=0x0) at ./V3Ast__gen_visitor.h:121
#16 0x0000000000470be7 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0xb81a10, vup=0x0) at ./V3Ast__gen_visitor.h:113
#17 0x0000000000470b67 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0xb81a10, vup=0x0) at ./V3Ast__gen_visitor.h:111
#18 0x0000000000470ba7 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0xb81a10, vup=0x0) at ./V3Ast__gen_visitor.h:112
#19 0x000000000046f1a7 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0xb81a10, vup=0x0) at ./V3Ast__gen_visitor.h:7
#20 0x0000000000436ce1 in AstAnd::accept (this=0xb81a10, v=..., vup=0x0) at ../V3AstNodes.h:2778
#21 0x00000000004816fb in AstNode::iterateAndNext (this=0xb81a10, v=..., vup=0x0) at ../V3Ast.cpp:772
#22 0x0000000000481575 in AstNode::iterateChildren (this=0xb813a0, v=..., vup=0x0) at ../V3Ast.cpp:754
#23 0x00000000005d39de in SliceVisitor::visit (this=0x7fffffffd670, nodep=0xb813a0) at ../V3Slice.cpp:482
#24 0x0000000000470de7 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0xb813a0, vup=0x0) at ./V3Ast__gen_visitor.h:121
#25 0x0000000000470be7 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0xb813a0, vup=0x0) at ./V3Ast__gen_visitor.h:113
#26 0x0000000000470b67 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0xb813a0, vup=0x0) at ./V3Ast__gen_visitor.h:111
#27 0x0000000000470ba7 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0xb813a0, vup=0x0) at ./V3Ast__gen_visitor.h:112
#28 0x0000000000471167 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0xb813a0, vup=0x0) at ./V3Ast__gen_visitor.h:135
#29 0x00000000004368c1 in AstOr::accept (this=0xb813a0, v=..., vup=0x0) at ../V3AstNodes.h:2766
#30 0x00000000004816fb in AstNode::iterateAndNext (this=0xb813a0, v=..., vup=0x0) at ../V3Ast.cpp:772
#31 0x000000000048154d in AstNode::iterateChildren (this=0xb812e0, v=..., vup=0x0) at ../V3Ast.cpp:753
#32 0x00000000005d35c2 in SliceVisitor::findImplicit (this=0x7fffffffd670, nodep=0xb812e0) at ../V3Slice.cpp:414
#33 0x00000000005d3642 in SliceVisitor::visit (this=0x7fffffffd670, nodep=0xb812e0) at ../V3Slice.cpp:422
#34 0x000000000046f3a7 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0xb812e0, vup=0x0) at ./V3Ast__gen_visitor.h:15
#35 0x000000000042be5f in AstAssignW::accept (this=0xb812e0, v=..., vup=0x0) at ../V3AstNodes.h:1359
#36 0x00000000004816fb in AstNode::iterateAndNext (this=0xb780d0, v=..., vup=0x0) at ../V3Ast.cpp:772
#37 0x0000000000481575 in AstNode::iterateChildren (this=0xb77b70, v=..., vup=0x0) at ../V3Ast.cpp:754
#38 0x00000000005d39de in SliceVisitor::visit (this=0x7fffffffd670, nodep=0xb77b70) at ../V3Slice.cpp:482
#39 0x0000000000471a67 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0xb77b70, vup=0x0) at ./V3Ast__gen_visitor.h:171
#40 0x000000000048ad87 in AstScope::accept (this=0xb77b70, v=..., vup=0x0) at ../V3AstNodes.h:788
#41 0x00000000004816fb in AstNode::iterateAndNext (this=0xb77b70, v=..., vup=0x0) at ../V3Ast.cpp:772
#42 0x0000000000481575 in AstNode::iterateChildren (this=0xb77600, v=..., vup=0x0) at ../V3Ast.cpp:754
#43 0x00000000005d39de in SliceVisitor::visit (this=0x7fffffffd670, nodep=0xb77600) at ../V3Slice.cpp:482
#44 0x0000000000471fe7 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0xb77600, vup=0x0) at ./V3Ast__gen_visitor.h:193
#45 0x00000000005cb9fd in AstTopScope::accept (this=0xb77600, v=..., vup=0x0) at ../V3AstNodes.h:816
#46 0x00000000004816fb in AstNode::iterateAndNext (this=0xaaa6f0, v=..., vup=0x0) at ../V3Ast.cpp:772
#47 0x0000000000481575 in AstNode::iterateChildren (this=0xaaa530, v=..., vup=0x0) at ../V3Ast.cpp:754
#48 0x00000000005d39de in SliceVisitor::visit (this=0x7fffffffd670, nodep=0xaaa530) at ../V3Slice.cpp:482
#49 0x0000000000470e27 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0xaaa530, vup=0x0) at ./V3Ast__gen_visitor.h:122
#50 0x0000000000470967 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0xaaa530, vup=0x0) at ./V3Ast__gen_visitor.h:102
#51 0x00000000004294c9 in AstModule::accept (this=0xaaa530, v=..., vup=0x0) at ../V3AstNodes.h:947
#52 0x00000000004816fb in AstNode::iterateAndNext (this=0xaaa530, v=..., vup=0x0) at ../V3Ast.cpp:772
#53 0x000000000048154d in AstNode::iterateChildren (this=0x982bb0, v=..., vup=0x0) at ../V3Ast.cpp:753
#54 0x00000000005d39de in SliceVisitor::visit (this=0x7fffffffd670, nodep=0x982bb0) at ../V3Slice.cpp:482
#55 0x0000000000470ae7 in AstNVisitor::visit (this=0x7fffffffd670, nodep=0x982bb0, vup=0x0) at ./V3Ast__gen_visitor.h:108
#56 0x000000000046e8cf in AstNetlist::accept (this=0x982bb0, v=..., vup=0x0) at ../V3AstNodes.h:3701
#57 0x00000000005d3a67 in SliceVisitor::SliceVisitor (this=0x7fffffffd670, rootp=0x982bb0) at ../V3Slice.cpp:490
#58 0x00000000005d164a in V3Slice::sliceAll (rootp=0x982bb0) at ../V3Slice.cpp:500
#59 0x000000000046a761 in process () at ../Verilator.cpp:300
#60 0x000000000046d90b in main (argc=5, argv=0x7fffffffe218, env=0x7fffffffe248) at ../Verilator.cpp:617
%Error: export VERILATOR_ROOT=
%Error: gdb verilator_bin_dbg --batch --quiet --return-child-result -ex 'run --cc aaa.v --debug --gdbbt' -ex 'set width 0' -ex 'bt'
%Error: Command Failed gdb verilator_bin_dbg --batch --quiet --return-child-result -ex 'run --cc aaa.v --debug --gdbbt' -ex 'set width 0' -ex 'bt'