Verilog-mode

Hmm.

I tried your example several ways and it seems consistently correct (and I have modules that use this technique too.)

I also eyeballed the code, and it seems to call the function to scan the auto_lisp's in the right place, it seems simple enough (famous last words). BTW the rule is to evaluate all AUTO_LISPs from top to the current AUTOINST, your I1 inst will set it to "is" than override it with "was".

So, any idea what exact steps I can follow to reproduce this?

Also are you using GNU or Xemacs? Which version?

Out of band:

Maybe it's part of my setup. One thing I just remembered is that some of the strangeness seemed to start after I changed my verilog-auto-save-policy to 'force'. I'll see if changing it back to 'auto' makes any difference.

I am running GNU Emacs 21.4.1

I also see other strangeness, which may mean I have some vestiges of my previous version. I just upgraded from version 1.10, which has worked well for me for many years.

Just to confirm... changing my auto-save-policy seems to have made the difference. Changed it to 'detect', not 'auto'. whoops. Anyway it may simply be an issue with the force.

One additional think I had noticed about using 'force' is that if I ran autos (C-c C-a) and then saved, it would expand autos the first time and delete them on the save.

If you can tell me what to type with force set that will show it, I'll still try to fix it. Even with force set here I'm not hitting it.

Simply typing C-k to remove the autos and C-s to expand and save them over and over (for me) causes the failure sometimes, and sometimes it gets it right. In fact, I have noticed that AUTOINPUT and AUTOOUTPUT sometimes fail with this version... again in MY environment.

I will spend some time trying to debug this when I get a moment. For now I have had to back up to version 1.10 which is rock solid.

I'm guessing this might have been fixed with rev698. Please give it a try.

Yes, this indeed appears to be fixed with verilog-mode 699. Thanks for updating me.

This is such an invaluable tool, I appreciate your willingness to support it.

I did have one initial issue, I had my hwdbg-verilog-before-auto-hook start failing with the message:

progn: autolisp_inst.v:1: Internal problem; use of syntax-ppss when cache may be corrupt

I commented out the code that was generating it, and it passes now. However, I'm clearly concerned it may cause me issues down the road. I'm not familiar with syntax-ppss. Is there something I can do to avoid this?

---- edit ----

(defun verilog-syntax-ppss (&optional pos) ;; (when verilog-no-change-functions ;; (backtrace) ;; (error "%s: Internal problem; use of syntax-ppss when cache may be corrupt" ;; (verilog-point-text))) (if (fboundp 'syntax-ppss) (syntax-ppss pos) (parse-partial-sexp (point-min) (or pos (point)))))

Uncommenting that should be ok, but it should also be impossible to get it outside of AUTO guts, as it's something I added for internal debugging. Can you determine the specific steps that got you to get the message so I can reproduce it? One thing that probably would help would be to post the backtrace it prints out. Thanks.

Just add the following hook to your .emacs file:

;;
;; Verilog HWDBG AUTO hook
;;
(defun hwdbg-verilog-before-auto-hook ()
  "Create output ports for hwdbg tagged wires/regs" 

  ;; Remove the previous
  (verilog-auto-re-search-do "/\\*AUTO_HWDBG\\*/" 'verilog-delete-autos-lined)

  ;; Find the AUTO_HWDBG tag
  (goto-char (point-min))
  (if (re-search-forward "/\\*AUTO_HWDBG\\*/" nil t)

      (let ((lastlineno 0) 
            (template-line 0) 
            (assigns-line 0) 
            (insert-len 0)
            (indent-pt (current-indentation)))

        (forward-line 1)
        (verilog-insert-indent "// Beginning of automatic HWDBG Port insertion\n")
        (setq template-line (point))
        (newline)
        (verilog-insert-indent "// hardware debug auto-assignments\n")
        (setq assigns-line (point))
        (newline)
        (verilog-insert-indent "// End of automatics\n")

        ;; start from the beginning again
        (goto-char (point-min))

        ;; now find all of the flagged wires and regs
        (while (re-search-forward "\\(wire\\|reg\\)\\ +\\(\\[.*:.*\\]\\)? +\\(.*\\)\; +/\\*HWDBG\\*/" nil t)

          (setq hwdbg-signal-string (match-string 3))
          (setq hwdbg-vector-string (match-string 2))
          (setq lastlineno (point))

          ;;<<<< insert the dbg_ rename assignment >>>>
          (goto-char assigns-line)
          (insert (concat "assign dbg_" hwdbg-signal-string " = " hwdbg-signal-string ";"))
          (electric-verilog-tab)
          (setq insert-len (- (line-end-position) (line-beginning-position)))
          ;;    adjust the end point
          (setq lastlineno (+ lastlineno insert-len 1))
          (end-of-line)
          (newline)
          (setq assigns-line (point))

          ;;<<<< insert the output decl >>>>
          (goto-char template-line)
          (insert (concat "output" hwdbg-vector-string "  dbg_" hwdbg-signal-string ";"))
          (electric-verilog-tab)
          ;;    figure out how much we just added
          (setq insert-len (- (line-end-position) (line-beginning-position)))
          (end-of-line)
          (newline)
          (setq template-line (point))
          ;;    adjust our assigns-line and lastlineno points
          (setq assigns-line (+ assigns-line insert-len 1))
          (setq lastlineno (+ lastlineno insert-len 1))

          ;; go back just past the last signal we worked on
          (goto-char lastlineno)
          )

        )
    )
  )

Then auto the following:

module autolisp_inst (/*AUTOARG*/);

   input       portA;
   input [3:0] busA;
   input       portB;
   input [1:0] busB;

   output      result;

   /*AUTO_HWDBG*/

   wire        a;
   wire        b; /*HWDBG*/
   wire [1:0]  c; /*HWDBG*/
   reg [3:0]   big_long_verilog_name; /*HWDBG*/

endmodule // autolisp_inst

I will try to get you the backtrace if you don't run into this. About any way I attempted to do the indentation runs into it.

Thanks again for taking the time to look into this.

I can live without the indentation if it becomes difficult to support. It's just beatuification. I tried to figure out other ways of getting the indentation to work, but your code is way beyond my skills. The (electric-verilog-tab) function has always been kind of 'magic' to me because it works so well.

If it works to simply disable the cache before evaluating hooks, esp. this particular hook (hwdbg-verilog-before-auto-hook) that is run before you have even populated the cache, then that would be great too. What I typically do with hooks can afford any slowdown disabling the cache may cause. I can't speak to the many others who may be affected by this. My guess, though, is that most engineers understand that hooks don't run at the same performance level as the core code.

Please try rev702. This version should not report the error in hooks, and instead cleanup the cache.