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Issue #358
verilog-auto-inst variable to control sorting ports in AUTOINST
| Status: | Closed | Start date: | 06/13/2011 | |
|---|---|---|---|---|
| Priority: | Normal | Due date: | ||
| Assignee: | Wilson Snyder | % Done: | 0% |
|
| Category: | Autos | |||
| Target version: | - |
Description
I'd like to ability to sort the ports listed in an AUTOINST.
I see a variable verilog-auto-arg-sort, but this has no effect on any AUTOINST's of a module with the variable set. This is probably because the AUTOINST uses the port declaration order, and not the AUTOARG order (which makes sense).
I can imagine this being implemented as:- A single variable to control all AUTOINST's in the file.
- A variable that could be set inside of each instantiated module, much like verilog-auto-arg-sort, such that anywhere the file was instantiated the ports would be sorted.
I can see benefits to both options, but #1 is probably easier to implement.
Suggested variable name:- verilog-auto-inst-sort
History
Updated by Brad Dobbie almost 2 years ago
I forgot to set some of the info above:
- Assignee: Wilson Snyder
- Category: Autos
Updated by Wilson Snyder almost 2 years ago
- Category set to Autos
- Status changed from New to Closed
- Assignee set to Wilson Snyder
Added to rev688 as verilog-auto-inst-sort, also added it for AUTOINSTPARAM.
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