verilog-auto-inst variable to control sorting ports in AUTOINST
|Assignee:||Wilson Snyder||% Done:|
I'd like to ability to sort the ports listed in an AUTOINST.
I see a variable verilog-auto-arg-sort, but this has no effect on any AUTOINST's of a module with the variable set. This is probably because the AUTOINST uses the port declaration order, and not the AUTOARG order (which makes sense).I can imagine this being implemented as:
- A single variable to control all AUTOINST's in the file.
- A variable that could be set inside of each instantiated module, much like verilog-auto-arg-sort, such that anywhere the file was instantiated the ports would be sorted.
I can see benefits to both options, but #1 is probably easier to implement.Suggested variable name: