Verilog-Perl

BTW covergroup/endgroup now in git towards 3.308.

Thanks for this quick response.

I should have written a reproducer from the start, but was just busy today -- my apologies. Consider the verilog below. These are the args to the var callbacks I see when it gets parsed.

Note the coverGroupInst has no data_type value at all. It would be useful if it could be 'covergroup' (similar to 'struct').

[K: var][N: myReg][O: module][N: ][D: reg][A: ]
[K: var][N: fooA][O: class][N: ][D: reg][A: ]
[K: member][N: structA][O: struct][N: ][D: reg][A: ]
[K: typedef][N: myStruct][O: module][N: ][D: struct][A: ]
[K: var][N: myEvent][O: module][N: ][D: event][A: ]
[K: var][N: fooInst][O: module][N: ][D: myFoo][A: ]
[K: var][N: structInst][O: module][N: ][D: myStruct][A: ]
[K: var][N: coverGroupInst][O: module][N: ][D: ][A: ]

 module gc;

    reg myReg;

    class myFoo;
        reg fooA;
    endclass

    typedef struct
    {
        reg structA;
    } myStruct;

    event myEvent;

    covergroup  myCoverGroup @(myEvent);

    myCoverPoint: coverpoint myReg
    {
        bins A = {1'b0};
        bins B = {1'b1};
    }

    endgroup // myCoverGroup

    myFoo fooInst = new;
    myStruct structInst;
    myCoverGroup coverGroupInst = new;

endmodule

Perfect, thanks!