Verilator

the following will not compile, i.e., such constructs work with logic/wire, but not with inout

// pseudo-code
module instantiator_thing ( inout [63:0] foo [5] )
generate begin
   for( i = 0; i < 5; i++ ) begin
      instantiated_thing u_thing( foo[i] );
   end
end
endmodule